Template Version: @(#)sac_nextcase 1.55 08/11/04 SMI
1. Introduction
    1.1. Project/Component Working Name:
	 Amendment to PCI-Express Binding

    1.2. Name of Document Author/Supplier:
	 Author:  Stephen Kelly

    1.3  Date of This Document:
	 27 September, 2005

    1.4. Name of Major Document Customer(s)/Consumer(s):
	 OpenBoot Firmware

2. Project Summary
   2.1. Project Description

	Add devsel-speed, udf-supported, cache-line-size, and latency-timer
	to the list of "Non PCI Express specific properties to be removed"
	in section 6 of the PCI-Express binding (FWARC case 2003/637)

	All four of these properties are based on register values that
	are either reserved or explicitly stated to have no impact on PCI
	Express device functionality.
   
   2.2. Risks and Assumptions
        N/A

3. Business Summary
   3.1. Problem Area
	These properties are no longer relevant to the PCI-Express architecture
	and therefore need not be exported.

   3.2. Market/Requester
	End-Users, Operations, Manufacturing, OS

   3.3. Business Justification
	Add correctness to the PCI Express Binding (FWARC/2003/637).

   3.4. Competitive Analysis
	N/A

   3.5. Opportunity Window/Exposure
	This needs to be corrected as soon as possible.

4. Technical Description

   No longer export these legacy PCI properties:

	udf-supported
	devsel-timing
	cache-line-size
	latency-timer

   on PCI Express devices as the properties are no longer relevant
   in the PCI Express architecture.

   udf-supported
   -------------	
   UDF Supported Bit: 
     Reserved in PCI Express

   devsel-speed
   ------------
   DEVSEL Timing Bits: 
     Do not apply to PCI Express and must be 0

   cache-line-size
   ---------------
   Bridge Cache Line Size Register: 
     This field is implemented by PCI Express devices as a read-write field for
     legacy compatibility purposes but has no impact on any PCI Express device 
     functionality  

   latency-timer
   -------------
   Bridge Latency Timer Register: 
     This register does not apply to PCI Express and must be read-only and
     hardwired to 0


5. Reference Documents

   PCI Bus Binding to IEEE Std 1275-1994 Revision 2.1

   PCI Express Binding to IEEE Std 1275-1994 Revision 1.8


6. Resources and Schedule
   6.1. Projected Availability
        Q2FY05

   6.2. Cost of Effort
        N/A

   6.3. Cost of Capital Resources
        N/A

7. Prototype Availability
   7.1. Prototype Availability
        N/A

   7.2. Prototype Cost
        N/A

6. Resources and Schedule
    6.4. Steering Committee requested information

       6.4.1. Consolidation C-team Name:
        Openboot

    6.5. ARC review type: FastTrack