Template Version: @(#)onepager.txt 1.34 07/08/27 SMI

Copyright 2007 Sun Microsystems

1. Introduction
   1.1. Project/Component Working Name:

	Mini MD

   1.2. Name of Document Author/Supplier:

	Fred Gotwald

   1.3. Date of This Document:

	10/11/2007

   1.4. Name of Major Document Customer(s)/Consumer(s):
	1.4.1. The PAC or CPT you expect to review your project:

		

	1.4.2. The ARC(s) you expect to review your project:

		FWARC

	1.4.3. The Director/VP who is "Sponsoring" this project:

		Michael.Sanfratello@Sun.COM

	1.4.4. The name of your business unit:

		Software

   1.5. Email Aliases:
    	1.5.1. Responsible Manager: chad.solomon@sun.com
    	1.5.2. Responsible Engineer: fred.gotwald@sun.com
    	1.5.3. Marketing Manager: 
	1.5.4. Interest List:	vbsc-dev@sun.com
				hvreview@sun.com

2. Project Summary
   2.1. Project Description:

	This project revises an undocumented interface between vbsc
	and hypervisor. Specifically, it provides a mechanism to download
	initial data used by hypervisor in machine desciption format.

   2.2. Risks and Assumptions:

	A flag day will be required between vbsc and hypervisor.

3. Business Summary
   3.1. Problem Area:

	This project removes hard-coded SRAM offsets from hypervisor
	and moves hypervisor-specific information from the existing
	hypervisor machine description to a new "mini" machine description.
	
	This improves the maintainability of the source code while improving
	support for future platforms.

   3.2. Market/Requester:

	Requested by the Maramba engineering development team.

   3.3. Business Justification:

	Reduces the life-cycle cost of multiple products by reducing the amount
	of future code changes required in hypervisor.

   3.4. Competitive Analysis:

   3.5. Opportunity Window/Exposure:

   3.6. How will you know when you are done?:

	Existing N1 and N2 platforms pass quality testing with no regressions
	found and the code changes are integrated into the corresponding
	release engineering gates.

4. Technical Description:
    4.1. Details:

	This project re-introduces a bootload mechanism that existed
	in early versions of vbsc. The mechanism consists of two parts,
	one in vbsc and one in the reset code on the host. Based on
	a command in the sequencer, vbsc will copy data to the SRAM in
	the FPGA, then notify the reset code. The reset code reads the
	data from the SRAM, copies it into the host DRAM, then acknowledges
	completion back to vbsc. This handshaking sequence continues until
	all data has been copied to the DRAM.

	When the hypervisor starts, it uses the value of %g3 to retrieve
	the data that was downloaded. The data is considered transient, so
	hypervisor makes its own copy of it. The address space is reused by
	the existing subsequent MD downloads.

    4.2. Bug/RFE Number(s):

	6558874 support delivery of mini-md from vbsc to hv at poweron with
		hv-specific info
	6558875 support parsing of a mini-md from vbsc for hv-specific info
		to leave out of hv md 
    
    4.3. In Scope:

	Mechanism for downloading data contained in the mini MD.

    4.4. Out of Scope:
	
	Documenting any existing vbsc-hypervisor interface which is unchanged
	by this project.
    
    4.5. Interfaces:

	The interface is Committed and will be introduced in a minor
	release of SysFW.

	The current register usage for the start of hypervisor is:

		%g1 Memory base address
		%g2 Hypervisor memory size
		%g3 Hypervisor machine description base address
		%g4 CPU start set
		%g5 Total memory size

	This project will revise the definition of %g3, %g4 and %g5 as
	follows:

		%g3 Mini machine description base address
		%g4 Unused
		%g5 Unused

	The original values contained in %g3, %g4, and %g5 will be contained
	in a platform_root node in the mini MD:

		node platform_root platform_root {
			hv_md = HVMDBASE;	// %g3 Platform-specific #define
			strand_startset = 0;	// %g4 Initialized at run-time
			total_physmem = 0;	// %g5 Initialized at run-time
			...
		}
    
    4.6. Doc Impact:

	None.
    
    4.7. Admin/Config Impact:

	None.
    
    4.8. HA Impact:

	None.
    
    4.9. I18N/L10N Impact:

	None.
    
    4.10. Packaging & Delivery:

	Will be delivered as part of a 7.1.x SysFW release.
    
    4.11. Security Impact:

	None.
    
    4.12. Dependencies:

	None.

5. Reference Documents:

	FWARC/2005/115  sun4v machine description

6. Resources and Schedule:
   6.1. Projected Availability:

	Prototype code is currently available and being code reviewed.

   6.2. Cost of Effort:
	
	Two people about 2 weeks.

   6.3. Cost of Capital Resources:

	N/A

   6.4. Product Approval Committee requested information:
   	6.4.1. Consolidation or Component Name:
	6.4.3. Type of CPT Review and Approval expected:
        6.4.4. Project Boundary Conditions:
	6.4.5. Is this a necessary project for OEM agreements:
	6.4.6. Notes:
	6.4.7. Target RTI Date/Release:

		October 2007

	6.4.8. Target Code Design Review Date:
	6.4.9. Update approval addition:

   6.5. ARC review type:

	FastTrack

   6.6. ARC Exposure:

	closed

       6.6.1. Rationale:

	Existing source code is not open.

7. Prototype Availability:
   7.1. Prototype Availability:

	Now.

   7.2. Prototype Cost:

	N/A