Copyright, 2007 Sun Microsystems Inc. All rights reserved. 0. Purpose This document specifies the interface that VBSC and POST use to pass information on the sun4v platforms. 0.1 Revision History ---------------------------------------------------------------------- | Version | Edited By | Changes ---------------------------------------------------------------------- | 1.1 | EBlanchard | Initial document creation ---------------------------------------------------------------------- 0.2 Contents 1. VBSC to POST interface 1.1 State of machine before POST begins 1.2 State of machine after POST has completed. 1.3 POST interface register usage 1.4 State of machine before returning to POST after a reconfig request. 1.5 VBSC actions on POST return 2. POST interface data 2.1 POST entry Info 2.1.3 Machine Information 2.1.3 Communication Information 2.1.3 POST runtime options 2.2 POST exit Info 3. Huron 3.1 Machine Summary 3.2 POST Interface Structure 3.3 POST Entry Words Formats 3.4 POST Results Words Formats 4. Glendale 4.1 Machine Summary 4.2 POST Interface Structure 4.3 POST Entry Words Formats 4.4 POST Results Words Formats 5. Monza 5.1 Machine Summary 5.2 POST Interface Structure 5.3 POST Entry Words Formats 5.4 POST Results Words Formats 6. Turgo 6.1 Machine Summary 6.2 POST Interface Structure 6.3 POST Entry Words Formats 6.4 POST Results Words Formats 7. Maramba 7.1 Machine Summary 7.2 POST Interface Structure 7.3 POST Entry Words Formats 7.4 POST Results Words Formats 8. Batoka 8.1 Machine Summary 8.2 POST Interface Structure 8.3 POST Entry Words Formats 8.4 POST Results Words Formats 0.3 References [1] FWARC Host Type Registry http://sac.eng.sun.com/arc/FWARC/Registries/Host_Type_Registry.txt [2] LDC Documents http://sac.sfbay/FWARC/2006/571/materials/ldc-link-protocol.v3.pdf http://sac.sfbay/FWARC/2006/055/commit2.materials/DomainServices-099.pdf [3] FMA Document http://sac.sfbay/PSARC/2002/412/final.materials/summary.txt 0.4 Glossary LDC - Logical Domain Channel. Described in [2] MCU - Memory Controller Unit. This is the basic hardware component that controls dimm access. The number of MCU's on a processor can vary by processor. NIU - Network Interface Unit PIU - PCI Express Unit SER - Service Error Report. This is the error reporting mechanism that FMA uses [3]. XAUI - Ten (Roman numeral) Attachment Unit Interface 1. VBSC to POST interface 1.1 Summary Before POST runs, VBSC sets up the POST Interface Structure in memory common to both POST and VBSC. VBSC and POST use this structure to communicate information between each other. The POST entry Info section of the interface structure is the information that VBSC passes to POST and the POST Return Info is the results that POST passes VBSC. The POST Entry Info includes the machine configuration, communication channel information, and POST runtime options. The POST Return Info includes the results from the tests that POST ran and the POST Exit Reason. The POST Interface Structure is designed so it can be used on multiple similar system architectures. All of the platforms that use this interface have the same generic entries in the POST Interface Structure, but the number and location of certain entries change depending on the platform or processor using it this interface. Section 2 of this document specifies all of the generic entries used in the interface. Starting at Section 3 and continuing to the end of the document, the sections define per platform the layout of the POST Interface Structure and bit definitions of platform dependent words. 1.2 POST interface register usage 1.2.1 POST return address When POST starts, %o7 contains the return address. POST jumps to this address in order to exit. 1.2.2 POST interface data. When POST starts, %g1 contains the physical address of the POST Interface Structure. 1.3 POST Exit Reason Definitions 1.3.1 Normal POST Exit POST completed normally. The POST results are valid. 1.3.2 POST Reconfiguration Request Exit POST requests a reconfigure and retest. The POST results are valid. VBSC must reconfigure the system based on POST results and the platform's system policy specification. After VBSC reconfigures the system, VBSC needs to run POST again. 1.3.3 POST does not return and times out POST no longer updates the progress pointer and is assumed to have hung. The POST test results are not valid. 1.3.4 POST returns an undefined exit_reason An unknown error has occurred. The POST test results are not vaild. 2. POST interface data All platforms use the following common data elements in their interface structures, although the ordering and number of the data elements is defined in the machine specific sections. 2.1 POST entry info 2.1.1 Machine Information 2.1.1.1 Thread Status | bits | number | field +----------+--------------+----------------------- | 63:0 | threads/64 | Thread Status 64 bit word that specifies the active threads that POST needs to test. The number of thread status words is platform specific since the number of thread status words that are in the POST interface data structure depends on how many threads are on the platform that POST is testing. These words contain a "1" in each bit for a CPU that is viable. thread_status0 contains bits for CPUs 0..63, bit0 => thread0 thread_status1 contains bits for CPUs 64..127, bit0 => thread64 thread_status[N] contains bits for CPUs (N*64)..(N*64 + 63) bit0 => thread(N*64) 2.1.1.2 MB Revision Number | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | MB Revision Number Mother board revision number stored in a 64 bit value. 2.1.1.3 Host Type | bits | number | field +----------+--------------+----------------------- | 32:0 | 1 | Host Type A 32 bit value that coresponds to the platform that POST runs on. The host type value is specified by the FWARC host type registry [1]. 2.1.1.4 MCU Info | bits | number | field +----------+--------------+----------------------- | 7:0 | # MCUs | MCU Info An 8 bit word that contains information about a specific MCU. There is one MCU Info field for each MCU in the platform, so the number of MCU Info bytes in the POST interface structure is platform specific. Some of the bits that can be contained in the MCU info are defined here: - Eight Bank Mode: This is a setting in the MCU of some CPUs. The bank setting descriptions can be found in the CPU's PRM. 2.1.1.5 XAUI Port Info | bits | number | field +----------+--------------+----------------------- | 7:0 | XAUI ports | XAUI Port Info An 8 bit word that contains information about a specific XAUI port. There is one XAUI port info field for each XAUI port in the platform, so the number of XAUI port info bytes in the POST interface structure is platform specific. 2.1.1.6 MAC Address | bits | number | field +----------+--------------+----------------------- | 63:0 | mac ports | MAC Address 64 bit word that contains a mac address. There is one MAC Address field for every mac address that VBSC needs to send POST. The number of MAC Address fields needed is platform specific. MAC address bit definitions: | bits | value +----------+-------------- | 7:0 | octet 1 | 15:8 | octet 2 | 23:16 | octet 3 | 31:24 | octet 4 | 39:32 | octet 5 | 47:40 | octet 6 | 63:48 | undefined 2.1.2 Communication Information 2.1.2.1 LDC qin | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | LDC qin 64 bit word that contains the physical base address of LDC input queue descriptor. 2.1.2.2 LDC qout | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | LDC qout 64 bit word that contains the physical base address of LDC output queue descriptor. 2.1.2.3 LDC qin data | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | LDC qin data 64 bit word that contains the physical base address for the LDC data input queue. 2.1.2.4 LDC qout data | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | LDC qout data 64 bit word that contains the physical base address for the LDC data output queue. 2.1.2.5 LDC qin nodeid | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | LDC qin nodeid 64 bit word that contains the physical base address for the LDC nodeid intput queue. 2.1.2.6 LDC qout nodeid | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | LDC qout nodeid 64 bit word that contains the physical base address for the LDC nodeid output queue. 2.1.2.7 LDC qin size | bits | number | field +----------+--------------+----------------------- | 7:0 | 1 | LDC qin size 8 bit value that contains the number of queue slots in LDC input queue. 2.1.2.8 LDC qout size | bits | number | field +----------+--------------+----------------------- | 7:0 | 1 | LDC qout size 8 bit value that contains the number of queue slots in LDC output queue. 2.1.2.9 Post XID | bits | number | field +----------+--------------+----------------------- | 7:0 | 1 | POST XID Xpar ID to be used for all service channel traffic to/from POST. 2.1.2.10 SER Address | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | Ser Address 64 bit word that contains the physical address where SER payload is written. 2.1.2.11 SER Size | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | Ser Size Size of SER payload area 2.1.2.12 SER Sid | bits | number | field +----------+--------------+----------------------- | 15:0 | 1 | Ser Sid 16 bit value that contains the Service ID to be used for the SER notification packet. 2.1.2.13 Progress Pointer | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | Progress Pointer 64 bit value that contains the Physical address of the 8-bit counter containing progress indication for VBSC. VBSC monitors this byte for changes. If the value of this byte does not change within sixty seconds, then VBSC will consider the host to be hung and will take appropriate action to recover. When Mode=menu VBSC does not implement a timeout. 2.1.3 POST Runtime Options 2.1.3.1 Verbosity | bits | number | field +----------+--------------+----------------------- | 7:0 | 1 | Verbosity An 8 bit value that indicates the POST verbosity level. The precise output for each level is determined by POST and is beyond the scope of this specification. Verbosity values 0 == None Only Error Messages 1 == Min Error + Minor Status 2 == Normal Status with a progress indicator 3 == Max Test status and info 4 == Debug Enable debug output 2.1.3.2 Level | bits | number | field +----------+--------------+----------------------- | 7:0 | 1 | Level An 8 bit value that indicates the POST testing level. The precise tests that are executed is determined by POST and is beyond the scope of this specification. Level values 0 == Min 1 == Max 2.1.3.3 Mode | bits | number | field +----------+--------------+----------------------- | 7:0 | 1 | Mode An 8 bit value that indicates the POST run mode. The details of what tests these modes will execute is negotiated between the OPS and POST project teams and is beyond the scope of this specification. Mode values 0 == Off 1 == Normal 2 == Service 3 == Menu 10 == OPS0 11 == OPS1 ... 41 == OPS31 Values from 10 to 41 (decimal) are reserved for the definition of OPS modes. 2.1.3.4 Entry reason | bits | number | field +----------+--------------+----------------------- | 7:0 | 1 | Entry Reason 8 bit value specifying the Reason for entering POST. Valid values are: 0 - normal POST entry 1 - restart POST after reset reconfig 2.2 POST exit info 2.2.1 Thread Results | bits | number | field +----------+--------------+----------------------- | 63:0 | threads/64 | Thread Results 64 bit word that contains the POST results for the processor threads. Each bit in this word corresponds to a thread. The bit to thread mapping is as follows: These words contain a "1" in each bit for a CPU that is viable. thread_status0 contains bits for CPUs 0..63, bit0 => thread0 thread_status1 contains bits for CPUs 64..127, bit0 => thread64 thread_status[N] contains bits for CPUs (N*64)..(N*64 + 63) bit0 => thread(N*64) The number of thread results words is platform specific since the number of thread status words that are in the POST interface data structure depends on how many threads are on the platform that POST is testing. 2.2.2 Processor Results | bits | number | field +----------+--------------+----------------------- | 63:0 | nodes | Processor Results 64 bit word that contains the POST results for devices in a processor that can be individually tested and disabled. Each bit in this word corresponds to a device. The bit to device mapping is platform specific and is defined in the corresponding platform section. This word contains a "0" for each bit corresponding to a device that failed POST. Bits corresponding to devices which are untested must be set to 1. Unused bits must be set to 1. The number of processor results words is platform specific since the number of processor results words that are in the POST interface data structure depends on how many nodes, processors, are on the platform that POST is testing. 2.2.3 IO Device Results | bits | number | field +----------+--------------+----------------------- | 63:0 | 1 | IO Device Results 64 bit word that contains the POST results for io devices. Each bit in this word corresponds to a device or is unused. The bit to device mapping is platform specific and is defined in the corresponding platform section. This word contains a "0" for each bit corresponding to an io device that failed POST. Bits corresponding to devices which are untested must be set to 1. Unused bits must be set to 1. 2.2.4 Dimm Results | bits | number | field +----------+--------------+----------------------- | 63:0 | nodes | Dimm Results 64 bit word that contains the POST results for dimms. Each bit in this word corresponds to a device or is unused. The bit to device mapping is platform specific and is defined in the corresponding platform section. This word contains a "0" for each bit corresponding to a dimm that failed POST. Bits corresponding to devices which are untested must be set to 1. Unused bits must be set to 1. 2.2.5 Exit Reason | bits | number | field +----------+--------------+----------------------- | 7:0 | 1 | Exit Reason 8 bit value containing the reason for exiting POST. Valid values are: 0 - Normal POST Exit 1 - POST Reconfiguration Request Exit 3. Huron 3.1 Machine Summary 3.1.1 Huron has 1 Node 3.1.2 Huron has 64 threads 3.1.3 Huron has 2 XAUI cards 3.1.4 Huron uses 4 MAC ports in POST 3.1.5 Huron has 4 MCUs 3.2 POST Interface Structure This is the format of the POST Interface Structure that is stored in the FPGA memory. This is not a packed structure. POST Entry Info: offset | bits | field -------+----------+-------------------- 0x00 | 63:0 | MB Revision Number 0x08 | 32:0 | Host Type 0x10 | 7:0 | Post XID 0x11 | 7:0 | Verbosity 0x12 | 7:0 | Level 0x13 | 7:0 | Mode 0x14 | 7:0 | Entry Reason 0x18 | 63:0 | Progress Pointer 0x20 | 63:0 | LDC qin 0x28 | 63:0 | LDC qout 0x30 | 63:0 | LDC qin data 0x38 | 63:0 | LDC qout data 0x40 | 63:0 | LDC qin nodeid 0x48 | 63:0 | LDC qout nodeid 0x50 | 7:0 | LDC qin size 0x51 | 7:0 | LDC qout size 0x58 | 63:0 | SER Address 0x60 | 15:0 | SER Size 0x62 | 7:0 | SER Sid 0x63 | 7:0 | MCU Info 0x64 | 7:0 | XAUI Port Info 1 0x65 | 7:0 | XAUI Port Info 2 0x68 | 63:0 | MAC Address 0 0x70 | 63:0 | MAC Address 1 0x78 | 63:0 | MAC Address 2 0x80 | 63:0 | MAC Address 3 0x88 | 63:0 | Thread Status POST Exit Info: offset | bits | field -------+----------+-------------------- 0x90 | 63:0 | IO Device Results 0x98 | 63:0 | Thread Results 0xa0 | 63:0 | Dimm Results 0xa8 | 63:0 | Processor Results 0xb0 | 7:0 | Exit Reason 3.3 POST Entry Words Formats 3.3.1 MCU Info MCU port info bit definitions: bit | value ------+-------------------- 0 | Eight Bank Mode 1-7 | undefined Eight Bank Mode: 0 = Normal Mode 1 = Eight Bank Mode 3.3.2 XAUI Port Info XAUI port info bit definitions: bit | value ------+-------------------- 0 | XAUI presence 1-7 | undefined XAUI presence bit: 0 = XAUI absent 1 = XAUI present 3.4 POST Results Words Formats 3.4.1 IO Device Results This is the bit to device mapping for the IO Device Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | XAUI_PORT0 1 | XAUI_PORT1 2 | PCISWITCH0 3 | PCISWITCH1 4 | PCISWITCH2 5 | PCISWITCH3 6 | GBEO 7 | GBE1 8 | PCIE-BRIDGE 9 | SASHBA 10-63 | Unused 3.4.2 Processor Results This is the bit to device mapping for the Processor Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | L2_BNK0 1 | L2_BNK1 2 | L2_BNK2 3 | L2_BNK3 4 | L2_BNK4 5 | L2_BNK5 6 | L2_BNK6 7 | L2_BNK7 8-31 | Unused 32 | PIU 33 | NIU_PORT0 34 | NIU_PORT1 35-63 | Unused 3.4.3 Dimm Results This is the bit to device mapping for the Dimm Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | BR0_CH0_DIMM0 1 | BR0_CH0_DIMM1 2 | BR0_CH1_DIMM0 3 | BR0_CH1_DIMM1 4 | BR1_CH0_DIMM0 5 | BR1_CH0_DIMM1 6 | BR1_CH1_DIMM0 7 | BR1_CH1_DIMM1 8 | BR2_CH0_DIMM0 9 | BR2_CH0_DIMM1 10 | BR2_CH1_DIMM0 11 | BR2_CH1_DIMM1 12 | BR3_CH0_DIMM0 13 | BR3_CH0_DIMM1 14 | BR3_CH1_DIMM0 15 | BR3_CH1_DIMM1 16-63 | Unused 4. Glendale 4.1 Machine Summary 4.1.1 Glendale has 1 Node 4.1.2 Glendale has 64 threads 4.1.3 Glendale has 2 XAUI cards 4.1.4 Glendale uses 4 MAC ports in POST 4.1.5 Glendale has 4 MCUs 4.2 POST Interface Structure This is the format of the POST Interface Structure that is stored in the FPGA memory. This is not a packed structure. POST Entry Info: offset | bits | field -------+----------+-------------------- 0x00 | 63:0 | MB Revision Number 0x08 | 32:0 | Host Type 0x10 | 7:0 | Post XID 0x11 | 7:0 | Verbosity 0x12 | 7:0 | Level 0x13 | 7:0 | Mode 0x14 | 7:0 | Entry Reason 0x18 | 63:0 | Progress Pointer 0x20 | 63:0 | LDC qin 0x28 | 63:0 | LDC qout 0x30 | 63:0 | LDC qin data 0x38 | 63:0 | LDC qout data 0x40 | 63:0 | LDC qin nodeid 0x48 | 63:0 | LDC qout nodeid 0x50 | 7:0 | LDC qin size 0x51 | 7:0 | LDC qout size 0x58 | 63:0 | SER Address 0x60 | 15:0 | SER Size 0x62 | 7:0 | SER Sid 0x63 | 7:0 | MCU Info 0x64 | 7:0 | XAUI Port Info 1 0x65 | 7:0 | XAUI Port Info 2 0x68 | 63:0 | MAC Address 0 0x70 | 63:0 | MAC Address 1 0x78 | 63:0 | MAC Address 2 0x80 | 63:0 | MAC Address 3 0x88 | 63:0 | Thread Status POST Exit Info: offset | bits | field -------+----------+-------------------- 0x90 | 63:0 | IO Device Results 0x98 | 63:0 | Thread Results 0xa0 | 63:0 | Dimm Results 0xa8 | 63:0 | Processor Results 0xb0 | 7:0 | Exit Reason 4.3 POST Entry Words Formats 4.3.1 MCU Info MCU port info bit definitions: bit | value ------+-------------------- 0 | Eight Bank Mode 1-7 | undefined Eight Bank Mode: 0 = Normal Mode 1 = Eight Bank Mode 4.3.2 XAUI Port Info XAUI port info bit definitions: bit | value ------+-------------------- 0 | XAUI presence 1-7 | undefined XAUI presence bit: 0 = XAUI absent 1 = XAUI present 4.4 POST Results Words Formats 4.4.1 IO Device Results This is the bit to device mapping for the IO Device Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | XAUI_PORT0 1 | XAUI_PORT1 2 | PCISWITCH0 3-5 | Unused 6 | GBEO 7 | Unused 8 | PCIE-BRIDGE 9 | REM 10 | USB0 11 | USB1 12 | DISPLAY 13-63 | Unused 4.4.2 Processor Results This is the bit to device mapping for the Processor Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | L2_BNK0 1 | L2_BNK1 2 | L2_BNK2 3 | L2_BNK3 4 | L2_BNK4 5 | L2_BNK5 6 | L2_BNK6 7 | L2_BNK7 8-31 | Unused 32 | PIU 33 | NIU_PORT0 34 | NIU_PORT1 35-63 | Unused 4.4.3 Dimm Results This is the bit to device mapping for the Dimm Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | BR0_CH0_DIMM0 1 | BR0_CH0_DIMM1 2 | BR0_CH1_DIMM0 3 | BR0_CH1_DIMM1 4 | BR1_CH0_DIMM0 5 | BR1_CH0_DIMM1 6 | BR1_CH1_DIMM0 7 | BR1_CH1_DIMM1 8 | BR2_CH0_DIMM0 9 | BR2_CH0_DIMM1 10 | BR2_CH1_DIMM0 11 | BR2_CH1_DIMM1 12 | BR3_CH0_DIMM0 13 | BR3_CH0_DIMM1 14 | BR3_CH1_DIMM0 15 | BR3_CH1_DIMM1 16-63 | Unused 5. Monza 5.1 Machine Summary 5.1.1 Monza has 1 Node 5.1.2 Monza has 64 threads 5.1.3 Monza has 2 XAUI cards 5.1.4 Monza uses 4 MAC ports in POST 5.1.5 Monza has 4 MCUs 5.2 POST Interface Structure This is the format of the POST Interface Structure that is stored in the FPGA memory. This is not a packed structure. POST Entry Info: offset | bits | field -------+----------+-------------------- 0x00 | 63:0 | MB Revision Number 0x08 | 32:0 | Host Type 0x10 | 7:0 | Post XID 0x11 | 7:0 | Verbosity 0x12 | 7:0 | Level 0x13 | 7:0 | Mode 0x14 | 7:0 | Entry Reason 0x18 | 63:0 | Progress Pointer 0x20 | 63:0 | LDC qin 0x28 | 63:0 | LDC qout 0x30 | 63:0 | LDC qin data 0x38 | 63:0 | LDC qout data 0x40 | 63:0 | LDC qin nodeid 0x48 | 63:0 | LDC qout nodeid 0x50 | 7:0 | LDC qin size 0x51 | 7:0 | LDC qout size 0x58 | 63:0 | SER Address 0x60 | 15:0 | SER Size 0x62 | 7:0 | SER Sid 0x63 | 7:0 | MCU Info 0x64 | 7:0 | XAUI Port Info 1 0x65 | 7:0 | XAUI Port Info 2 0x68 | 63:0 | MAC Address 0 0x70 | 63:0 | MAC Address 1 0x78 | 63:0 | MAC Address 2 0x80 | 63:0 | MAC Address 3 0x88 | 63:0 | Thread Status POST Exit Info: offset | bits | field -------+----------+-------------------- 0x90 | 63:0 | IO Device Results 0x98 | 63:0 | Thread Results 0xa0 | 63:0 | Dimm Results 0xa8 | 63:0 | Processor Results 0xb0 | 7:0 | Exit Reason 5.3 POST Entry Words Formats 5.3.1 MCU Info MCU port info bit definitions: bit | value ------+-------------------- 0 | Eight Bank Mode 1-7 | undefined Eight Bank Mode: 0 = Normal Mode 1 = Eight Bank Mode 5.3.2 XAUI Port Info XAUI port info bit definitions: bit | value ------+-------------------- 0 | XAUI presence 1-7 | undefined XAUI presence bit: 0 = XAUI absent 1 = XAUI present 5.4 POST Results Words Formats 5.4.1 IO Device Results This is the bit to device mapping for the IO Device Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | XAUI_PORT0 1 | XAUI_PORT1 2 | PCISWITCH0 3-5 | Unused 6 | GBEO 7 | GBE1 8 | PCIE-BRIDGE 9 | Unused 10 | USB 11-12 | Unused 13 | GBE2 14 | RTM 15-63 | Unused 5.4.2 Processor Results This is the bit to device mapping for the Processor Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | L2_BNK0 1 | L2_BNK1 2 | L2_BNK2 3 | L2_BNK3 4 | L2_BNK4 5 | L2_BNK5 6 | L2_BNK6 7 | L2_BNK7 8-31 | Unused 32 | PIU 33 | NIU_PORT0 34 | NIU_PORT1 35-63 | Unused 5.4.3 Dimm Results This is the bit to device mapping for the Dimm Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | BR0_CH0_DIMM0 1 | BR0_CH0_DIMM1 2 | BR0_CH1_DIMM0 3 | BR0_CH1_DIMM1 4 | BR1_CH0_DIMM0 5 | BR1_CH0_DIMM1 6 | BR1_CH1_DIMM0 7 | BR1_CH1_DIMM1 8 | BR2_CH0_DIMM0 9 | BR2_CH0_DIMM1 10 | BR2_CH1_DIMM0 11 | BR2_CH1_DIMM1 12 | BR3_CH0_DIMM0 13 | BR3_CH0_DIMM1 14 | BR3_CH1_DIMM0 15 | BR3_CH1_DIMM1 16-63 | Unused 6. Turgo 6.1 Machine Summary 6.1.1 Turgo has 1 Node 6.1.2 Turgo has 64 threads 6.1.3 Turgo has 2 XAUI cards 6.1.4 Turgo uses 4 MAC ports in POST 6.1.5 Turgo has 4 MCUs 6.2 POST Interface Structure This is the format of the POST Interface Structure that is stored in the FPGA memory. This is not a packed structure. POST Entry Info: offset | bits | field -------+----------+-------------------- 0x00 | 63:0 | MB Revision Number 0x08 | 32:0 | Host Type 0x10 | 7:0 | Post XID 0x11 | 7:0 | Verbosity 0x12 | 7:0 | Level 0x13 | 7:0 | Mode 0x14 | 7:0 | Entry Reason 0x18 | 63:0 | Progress Pointer 0x20 | 63:0 | LDC qin 0x28 | 63:0 | LDC qout 0x30 | 63:0 | LDC qin data 0x38 | 63:0 | LDC qout data 0x40 | 63:0 | LDC qin nodeid 0x48 | 63:0 | LDC qout nodeid 0x50 | 7:0 | LDC qin size 0x51 | 7:0 | LDC qout size 0x58 | 63:0 | SER Address 0x60 | 15:0 | SER Size 0x62 | 7:0 | SER Sid 0x63 | 7:0 | MCU Info 0x64 | 7:0 | XAUI Port Info 1 0x65 | 7:0 | XAUI Port Info 2 0x68 | 63:0 | MAC Address 0 0x70 | 63:0 | MAC Address 1 0x78 | 63:0 | MAC Address 2 0x80 | 63:0 | MAC Address 3 0x88 | 63:0 | Thread Status POST Exit Info: offset | bits | field -------+----------+-------------------- 0x90 | 63:0 | IO Device Results 0x98 | 63:0 | Thread Results 0xa0 | 63:0 | Dimm Results 0xa8 | 63:0 | Processor Results 0xb0 | 7:0 | Exit Reason 6.3 POST Entry Words Formats 6.3.1 MCU Info MCU port info bit definitions: bit | value ------+-------------------- 0 | Eight Bank Mode 1-7 | undefined Eight Bank Mode: 0 = Normal Mode 1 = Eight Bank Mode 6.3.2 XAUI Port Info XAUI port info bit definitions: bit | value ------+-------------------- 0 | XAUI presence 1-7 | undefined XAUI presence bit: 0 = XAUI absent 1 = XAUI present 6.4 POST Results Words Formats 6.4.1 IO Device Results This is the bit to device mapping for the IO Device Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | XAUI_PORT0 1 | XAUI_PORT1 2 | PCISWITCH0 3 | PCISWITCH1 4 | PCISWITCH2 5 | PCISWITCH3 6 | GBEO 7 | GBE1 8 | PCIE-BRIDGE 9 | SASHBA 10-14 | Unused 15 | PCIE-BRIDGE2 10-63 | Unused 6.4.2 Processor Results This is the bit to device mapping for the Processor Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | L2_BNK0 1 | L2_BNK1 2 | L2_BNK2 3 | L2_BNK3 4 | L2_BNK4 5 | L2_BNK5 6 | L2_BNK6 7 | L2_BNK7 8-31 | Unused 32 | PIU 33 | NIU_PORT0 34 | NIU_PORT1 35-63 | Unused 6.4.3 Dimm Results This is the bit to device mapping for the Dimm Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | BR0_CH0_DIMM0 1 | BR0_CH0_DIMM1 2 | BR0_CH1_DIMM0 3 | BR0_CH1_DIMM1 4 | BR1_CH0_DIMM0 5 | BR1_CH0_DIMM1 6 | BR1_CH1_DIMM0 7 | BR1_CH1_DIMM1 8 | BR2_CH0_DIMM0 9 | BR2_CH0_DIMM1 10 | BR2_CH1_DIMM0 11 | BR2_CH1_DIMM1 12 | BR3_CH0_DIMM0 13 | BR3_CH0_DIMM1 14 | BR3_CH1_DIMM0 15 | BR3_CH1_DIMM1 16-63 | Unused 7. Maramba 7.1 Machine Summary 6.1.1 Maramba has 2 Nodes 6.1.2 Maramba has 128 threads 6.1.3 Maramba has 2 XAUI cards 6.1.4 Maramba uses 4 mac ports in POST 6.1.5 Maramba has 4 MCUs 7.2 POST Interface Structure This is the format of the POST Interface Structure that is stored in the FPGA memory. This is not a packed structure. POST Entry Info: offset | bits | field -------+----------+-------------------- 0x00 | 63:0 | MB Revision Number 0x08 | 63:0 | Host Type 0x10 | 7:0 | Post XID 0x11 | 7:0 | Verbosity 0x12 | 7:0 | Level 0x13 | 7:0 | Mode 0x14 | 7:0 | Entry Reason 0x18 | 63:0 | Progress Pointer 0x20 | 63:0 | LDC qin 0x28 | 63:0 | LDC qout 0x30 | 63:0 | LDC qin data 0x38 | 63:0 | LDC qout data 0x40 | 63:0 | LDC qin nodeid 0x48 | 63:0 | LDC qout nodeid 0x50 | 7:0 | LDC qin size 0x51 | 7:0 | LDC qout size 0x58 | 63:0 | SER Address 0x60 | 15:0 | SER Size 0x62 | 7:0 | SER Sid 0x63 | 7:0 | MCU Info 0x64 | 7:0 | XAUI Port Info 1 0x65 | 7:0 | XAUI Port Info 2 0x68 | 63:0 | MAC Address 0 0x70 | 63:0 | MAC Address 1 0x78 | 63:0 | MAC Address 2 0x80 | 63:0 | MAC Address 3 0x88 | 63:0 | Thread Status 0 0x90 | 63:0 | Thread Status 1 POST Exit Info: offset | bits | field -------+----------+-------------------- 0x98 | 63:0 | IO Device Results 0xa0 | 63:0 | Thread Results 0 0xa8 | 63:0 | Thread Results 1 0xb0 | 63:0 | Dimm Results 0 0xb8 | 63:0 | Dimm Results 1 0xc0 | 63:0 | Processor Results 0 0xc8 | 63:0 | Processor Results 1 0xd0 | 7:0 | Exit Reason 7.3 POST Entry Words Formats 7.3.1 MCU Info MCU port info bit definitions: bit | value ------+-------------------- 0 | Eight Bank Mode 1-7 | undefined Eight Bank Mode: 0 = Normal Mode 1 = Eight Bank Mode 7.3.2 XAUI Port Info XAUI port info bit definitions: bit | value ------+-------------------- 0 | XAUI presence 1-7 | undefined XAUI presence bit: 0 = XAUI absent 1 = XAUI present 7.4 POST Results Words Formats 7.4.1 IO Device Results This is the bit to device mapping for the IO Device Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | XAUI_PORT0 1 | XAUI_PORT1 2 | PCISWITCH0 3 | PCISWITCH1 4 | PCISWITCH2 5 | PCISWITCH3 6 | GBE 7 | PCIEIO 8 | SASHBA 9-63 | Unused 7.4.2 Processor Results This is the bit to device mapping for the Processor Results Words in the POST Exit Info portion of the POST Interface Structure. Processor Results 0 is for node 0 and Processor Results 1 if for node 1. bit | field ------+-------------------- 0 | L2_BNK0 1 | L2_BNK1 2 | L2_BNK2 3 | L2_BNK3 4 | L2_BNK4 5 | L2_BNK5 6 | L2_BNK6 7 | L2_BNK7 8-31 | Unused 32 | PIU 33-63 | Unused 7.4.3 Dimm Results This is the bit to device mapping for the Dimm Results Words in the POST Exit Info portion of the POST Interface Structure. Dimm Results 0 is for node 0 and Dimm Results 1 is for node 1. bit | field ------+-------------------- 0 | BR0_CH0_DIMM0 1 | BR0_CH0_DIMM1 2 | BR0_CH0_DIMM2 3 | BR0_CH0_DIMM3 4 | BR0_CH1_DIMM0 5 | BR0_CH1_DIMM1 6 | BR0_CH1_DIMM2 7 | BR0_CH1_DIMM3 8 | BR1_CH0_DIMM0 9 | BR1_CH0_DIMM1 10 | BR1_CH0_DIMM2 11 | BR1_CH0_DIMM3 12 | BR1_CH1_DIMM0 13 | BR1_CH1_DIMM1 14 | BR1_CH1_DIMM2 15 | BR1_CH1_DIMM3 16-63 | Unused 8. Batoka 8.1 Machine Summary 8.1.1 Batoka has 4 Nodes 8.1.2 Batoka has 256 threads 8.1.3 Batoka has 2 XAUI cards 8.1.4 Batoka uses 4 mac ports in POST 8.1.5 Batoka has 8 MCUs 8.2 POST Interface Structure This is the format of the POST Interface Structure that is stored in the FPGA memory. This is not a packed structure. POST Entry Info: offset | bits | field -------+----------+-------------------- 0x00 | 63:0 | MB Revision Number 0x08 | 63:0 | Host Type 0x10 | 7:0 | Post XID 0x11 | 7:0 | Verbosity 0x12 | 7:0 | Level 0x13 | 7:0 | Mode 0x14 | 7:0 | Entry Reason 0x18 | 63:0 | Progress Pointer 0x20 | 63:0 | LDC qin 0x28 | 63:0 | LDC qout 0x30 | 63:0 | LDC qin data 0x38 | 63:0 | LDC qout data 0x40 | 63:0 | LDC qin nodeid 0x48 | 63:0 | LDC qout nodeid 0x50 | 7:0 | LDC qin size 0x51 | 7:0 | LDC qout size 0x58 | 63:0 | SER Address 0x60 | 15:0 | SER Size 0x62 | 7:0 | SER Sid 0x63 | 7:0 | MCU Info 0x64 | 7:0 | XAUI Port Info 1 0x65 | 7:0 | XAUI Port Info 2 0x68 | 63:0 | MAC Address 0 0x70 | 63:0 | MAC Address 1 0x78 | 63:0 | MAC Address 2 0x80 | 63:0 | MAC Address 3 0x88 | 63:0 | Thread Status 0 0x90 | 63:0 | Thread Status 1 0x98 | 63:0 | Thread Status 2 0xa0 | 63:0 | Thread Status 3 POST Exit Info: offset | bits | field -------+----------+-------------------- 0xa8 | 63:0 | IO Device Results 0xb0 | 63:0 | Thread Results 0 0xb8 | 63:0 | Thread Results 1 0xc0 | 63:0 | Thread Results 2 0xc8 | 63:0 | Thread Results 3 0xd0 | 63:0 | Dimm Results 0 0xd8 | 63:0 | Dimm Results 1 0xe0 | 63:0 | Dimm Results 2 0xe8 | 63:0 | Dimm Results 3 0xf0 | 63:0 | Processor Results 0 0xf8 | 63:0 | Processor Results 1 0x100 | 63:0 | Processor Results 2 0x108 | 63:0 | Processor Results 3 0x110 | 7:0 | Exit Reason 8.3 POST Entry Words Formats 8.3.1 MCU Info MCU port info bit definitions: bit | value ------+-------------------- 0 | Eight Bank Mode 1-7 | undefined Eight Bank Mode: 0 = Normal Mode 1 = Eight Bank Mode 8.3.2 XAUI Port Info XAUI port info bit definitions: bit | value ------+-------------------- 0 | XAUI presence 1-7 | undefined XAUI presence bit: 0 = XAUI absent 1 = XAUI present 8.4 POST Results Words Formats 8.4.1 IO Device Results This is the bit to device mapping for the IO Device Results Word in the POST Exit Info portion of the POST Interface Structure. bit | field ------+-------------------- 0 | XAUI_PORT0 1 | XAUI_PORT1 2 | PCISWITCH0 3 | PCISWITCH1 4 | PCISWITCH2 5 | PCISWITCH3 6 | GBE 7 | PCIEIO 8 | SASHBA 9-63 | Unused 8.4.2 Processor Results This is the bit to device mapping for the Processor Results Words in the POST Exit Info portion of the POST Interface Structure. Processor Results 0 is for node 0 and Processor Results 1, 2, 3 are for nodes 1, 2, 3. bit | field ------+-------------------- 0 | L2_BNK0 1 | L2_BNK1 2 | L2_BNK2 3 | L2_BNK3 4 | L2_BNK4 5 | L2_BNK5 6 | L2_BNK6 7 | L2_BNK7 8-31 | Unused 32 | PIU 33-63 | Unused 8.4.3 Dimm Results This is the bit to device mapping for the Dimm Results Words in the POST Exit Info portion of the POST Interface Structure. Dimm Results 0 is for node 0 and Dimm Results 1, 2, 3 are for nodes 1, 2, 3. bit | field ------+-------------------- 0 | BR0_CH0_DIMM0 1 | BR0_CH0_DIMM1 2 | BR0_CH0_DIMM2 3 | BR0_CH0_DIMM3 4 | BR0_CH1_DIMM0 5 | BR0_CH1_DIMM1 6 | BR0_CH1_DIMM2 7 | BR0_CH1_DIMM3 8 | BR1_CH0_DIMM0 9 | BR1_CH0_DIMM1 10 | BR1_CH0_DIMM2 11 | BR1_CH0_DIMM3 12 | BR1_CH1_DIMM0 13 | BR1_CH1_DIMM1 14 | BR1_CH1_DIMM2 15 | BR1_CH1_DIMM3 16-63 | Unused