1c1
< Copyright, 2008 Sun Microsystems Inc. All rights reserved.
---
> Copyright, 2007 Sun Microsystems Inc. All rights reserved.
14d13
< | 1.2     | S.Jain     | Congo Platform added.
61,65d59
<     9. Congo
<        9.1 Machine Summary
<        9.2 POST Interface Structure
<        9.3 POST Entry Words Formats
<        9.4 POST Results Words Formats
1134,1138c1128,1132
<       7.1.1 Maramba has 2 Nodes
<       7.1.2 Maramba has 128 threads
<       7.1.3 Maramba has 2 XAUI cards
<       7.1.4 Maramba uses 4 mac ports in POST
<       7.1.5 Maramba has 4 MCUs
---
>       6.1.1 Maramba has 2 Nodes
>       6.1.2 Maramba has 128 threads
>       6.1.3 Maramba has 2 XAUI cards
>       6.1.4 Maramba uses 4 mac ports in POST
>       6.1.5 Maramba has 4 MCUs
1430,1586d1423
<       ------+--------------------
<         0   | BR0_CH0_DIMM0
<         1   | BR0_CH0_DIMM1
<         2   | BR0_CH0_DIMM2
<         3   | BR0_CH0_DIMM3
<         4   | BR0_CH1_DIMM0
<         5   | BR0_CH1_DIMM1
<         6   | BR0_CH1_DIMM2
<         7   | BR0_CH1_DIMM3
<         8   | BR1_CH0_DIMM0
<         9   | BR1_CH0_DIMM1
<        10   | BR1_CH0_DIMM2
<        11   | BR1_CH0_DIMM3
<        12   | BR1_CH1_DIMM0
<        13   | BR1_CH1_DIMM1
<        14   | BR1_CH1_DIMM2
<        15   | BR1_CH1_DIMM3
<       16-63 | Unused
< 
< 9. Congo
<       
<    9.1 Machine Summary
< 
<       9.1.1 Congo has 2 Nodes
<       9.1.2 Congo has 128 threads
<       9.1.3 Congo has 2 XAUI cards
<       9.1.4 Congo uses 4 mac ports in POST
<       9.1.5 Congo has 4 MCUs
< 
< 
<    9.2 POST Interface Structure
< 
<       This is the format of the POST Interface Structure that is stored in the
<       FPGA memory. This is not a packed structure.
< 
<       POST Entry Info:
< 
<       offset | bits     | field
<       -------+----------+--------------------
<       0x00   | 63:0     | MB Revision Number
<       0x08   | 63:0     | Host Type
<       0x10   | 7:0      | Post XID
<       0x11   | 7:0      | Verbosity
<       0x12   | 7:0      | Level
<       0x13   | 7:0      | Mode
<       0x14   | 7:0      | Entry Reason
<       0x18   | 63:0     | Progress Pointer
<       0x20   | 63:0     | LDC qin
<       0x28   | 63:0     | LDC qout
<       0x30   | 63:0     | LDC qin data
<       0x38   | 63:0     | LDC qout data
<       0x40   | 63:0     | LDC qin nodeid
<       0x48   | 63:0     | LDC qout nodeid
<       0x50   | 7:0      | LDC qin size
<       0x51   | 7:0      | LDC qout size
<       0x58   | 63:0     | SER Address
<       0x60   | 15:0     | SER Size
<       0x62   | 7:0      | SER Sid
<       0x63   | 7:0      | MCU Info
<       0x64   | 7:0      | XAUI Port Info 1
<       0x65   | 7:0      | XAUI Port Info 2
<       0x68   | 63:0     | MAC Address 0
<       0x70   | 63:0     | MAC Address 1
<       0x78   | 63:0     | MAC Address 2
<       0x80   | 63:0     | MAC Address 3
<       0x88   | 63:0     | Thread Status 0
<       0x90   | 63:0     | Thread Status 1
< 
<       POST Exit Info:
< 
<       offset | bits     | field
<       -------+----------+--------------------
<       0x98   | 63:0     | IO Device Results
<       0xa0   | 63:0     | Thread Results 0
<       0xa8   | 63:0     | Thread Results 1
<       0xb0   | 63:0     | Dimm Results 0
<       0xb8   | 63:0     | Dimm Results 1
<       0xc0   | 63:0     | Processor Results 0
<       0xc8   | 63:0     | Processor Results 1
<       0xd0   | 7:0      | Exit Reason
< 
<    9.3 POST Entry Words Formats 
<   
<    9.3.1 MCU Info
< 
<       MCU port info bit definitions:
< 
<       bit   |  value
<       ------+--------------------
<         0   | Eight Bank Mode
<        1-7  | undefined
< 
<          Eight Bank Mode:
<             0 = Normal Mode
<             1 = Eight Bank Mode
< 
<    9.3.2 XAUI Port Info
< 
<       XAUI port info bit definitions:
< 
<       bit   |  value
<       ------+--------------------
<         0   | XAUI presence
<        1-7  | undefined
< 
<       XAUI presence bit:
<          0 = XAUI absent
<          1 = XAUI present
< 
<    9.4 POST Results Words Formats
< 
<    9.4.1 IO Device Results
< 
<       This is the bit to device mapping for the IO Device Results Word in the
<       POST Exit Info portion of the POST Interface Structure.
<   
<       bit   |  field
<       ------+--------------------
<         0   | XAUI_PORT0
<         1   | XAUI_PORT1
<         2   | PCISWITCH0
<         3   | PCISWITCH1
<         4   | PCISWITCH2
<         5   | PCISWITCH3
<         6   | GBE
<         7   | PCIEIO
<         8   | SASHBA
<         9   | PCIE Bridge
<       10-63 | Unused
< 
<    9.4.2 Processor Results
< 
<       This is the bit to device mapping for the Processor Results Words in
<       the POST Exit Info portion of the POST Interface Structure. Processor
<       Results 0 is for node 0 and Processor Results 1 if for node 1.
< 
<       bit   |  field
<       ------+--------------------
<         0   | L2_BNK0
<         1   | L2_BNK1
<         2   | L2_BNK2
<         3   | L2_BNK3
<         4   | L2_BNK4
<         5   | L2_BNK5
<         6   | L2_BNK6
<         7   | L2_BNK7
<        8-31 | Unused
<        32   | PIU
<       33-63 | Unused
< 
<    9.4.3 Dimm Results
< 
<       This is the bit to device mapping for the Dimm Results Words in the
<       POST Exit Info portion of the POST Interface Structure. Dimm Results 0
<       is for node 0 and Dimm Results 1 is for node 1.
< 
<       bit   |  field