id: @(#)HWD.txt 1.16 08/02/15 purpose: Hardware Descriptor for OPL Project copyright: Copyright 2008 Sun Microsystems, Inc. All Rights Reserved copyright: Use is subject to license terms. Title: Hardware Descriptor table for OPL systems o PURPOSE Olympus Product Line (OPL) systems are being jointly developed by Sun & Fujitsu. The product line will include Olympus-C Processor (SPARC64-VI) and Jupiter processor (SPARC64-VII) based Data Center (DC), Form Factor (FF), and Ikkaku machines. This document defines the software interface between the POST, OBP and Solaris (IKP) for the OPL systems. POST, in collaboration with the Service Processor, will create a data structure that would define the domain hardware configuration, component status collected by POST, and other system information consumed by OBP & Solaris. This data structure is called the Hardware Descriptor table. This document will talk about the structure and fields of the Hardware Descriptor table. The process of creation of this table is out of scope of this document. TASK GROUP MEMBERS: The following individuals are the members of the task group that produced this document. Sunit Jain (CSW/OPL OBP) - Sun Microsystems, Inc. 1 OVERVIEW & REFERENCE This document describes the software interface between the POST, OBP & Solaris (IKP) for OPL systems. The interface is a data structure, called Hardware Descriptor table, that is created by POST & the Service Processor, & consumed by the OBP & Solaris. Each System Board (SB) has its own SRAM where the HW Descriptor pertaining to that SB would be saved. OBP & Solaris can access this Hardware Descriptor Table by accessing the SRAM. The SRAM is accessible from both the domain as well as from the Service Processor. 1.1 REFERENCES [1] Columbus2 Logical Specification Rev. 1.1 [2] Jupiter Bus bindings update FWARC/2007/411 http://sac.eng/Archives/CaseLog/arc/FWARC/2007/411/materials/ Jupiter Bus bindings update FWARC/2006/012 http://sac.eng/Archives/CaseLog/arc/FWARC/2006/012/materials/ Jupiter Bus bindings FWARC/2005/076 http://sac.eng/Archives/CaseLog/arc/FWARC/2005/076/commitment.materials/ 1.2 DEFINITION OF TERMS CAB Cacheable Address Block. Cacheable memory assigned to an XSB. Chunk A contiguous block of memory. CMU CPU & Memory Unit. Board with 4x CPUs, memory, SCs, CMU-CH, TOD, NVRAM, SCF interface, PROM. CMU-CH CPU Memory Unit Channel. PCI bus that supports Boot PROM, TOD/NVRAM, ESCF interface, Serial console. Part of SC. Floating boards System boards that can be moved around between different domains as and when needed. It is preferred that kernel & OBP are not placed on such boards. FMEM Flash Memory (OBP PROM) HWD Hardware Descriptor IOC IO Controller (Oberon) IOU IO Unit. IO board with 2x Oberons and other onboard devices like PCIE-PCIX bridge, SAS, GbE & PCIE/PCIX slots. Jupiter Bus System bus for OPL systems. Jupiter Processor Jupiter processor will have 2x Physical cores, each core with 4x Virtual strands. SPARC64-VII. LSB Logical System Board. An LSB could be a PSB or XSB. MAC Memory Access Controller (memory controller). MAC connects the SC with the memory modules. Performs memory access control, memory initialization & diagnostics. MAC Address Media Access Control (MAC address). Hardware address of a device connected to a shared network medium. Oberon Host-IO bridge. Provides PCI Express interface to the system bus. Olympus-C Olympus-C processor has 2x Physical cores, each core with 2x Virtual strands. SPARC64-VI. OPL Olympus Product Line PCI Peripheral Component Interconnect PCIE (or PCI-E) PCI Express PCIX (or PCI-X) eXtended PCI POST Power On Self Test PSB Physical System Board (a.k.a. SB) SB System Board - consists of 4x processors, 2x Oberon ASICs, 4x Memory controllers (each with upto 32 DIMMs) SC System Controller (not to be confused with Service Processor as in Starcat/Serengeti). It is responsible for routing the address/data between CPUs and memory controllers and the system crossbar. SCF System Controller Facility (a.k.a. Service Processor) SP Service Processor SRAM Static Random Access Memory XSB Extended System Board. A PSB can be logically partitioned into 4 XSBs. XSCF eXtended System Controller Facility 2 INTERFACE DETAILS Each LSB implements an SRAM on its CMU which contain domain related data. SRAM is divided info different sections - DSCP Interface Buffer, CMD Interface Buffer and Domain/SP SRAM Interface Buffer. DSCP Interface Buffer is used for the Domain-SP communication based on the DSCP protocol. CMD Interface Buffer is used for the mailbox communication between the Domain & SP. Domain/SP SRAM Interface Buffer is further divided into - Domain/SP SRAM Interface Buffer header, Hardware Descriptor, CPU Signature, OBP/POST/Driver Trace, OBP/POST work, etc. Out of all these, only the structure of Hardware Descriptor falls into the scope of this document and will be described in the following sections. DOMAIN A +--------------------------+--------------------------+ | | | | +-------------------+ | +-------------------+ | | | DSCP I/F Buffer | | | DSCP I/F Buffer | | | +-------------------+ | +-------------------+ | | | CMD I/F Buffer | | | CMD I/F Buffer | | @====> +-------------------+ | +-------------------+ <====@ | | Domain/SP | | | Domain/SP | | | | SRAM Interface | | | SRAM Interface | | | | Buffer | | | Buffer | | | +-------------------+ | +-------------------+ | | | | | LSB0 SRAM | LSB1 SRAM | +--------------------------+--------------------------+ LSB 0 LSB 1 @====> +--------------------------+ | Domain/SP SRAM Interface | | Buffer Header | #~~~~> +--------------------------+\ | Hardware Descriptor | | | (LSB Unit Information) | | Defined in this document | (Details below) | | +--------------------------+/ | CPU Signature | +--------------------------+ | OBP/POST/Driver Trace | +--------------------------+ | OBP/POST Work | +--------------------------+ | etc. ... | +--------------------------+ #~~~~> +----------------------------+ | Hardware Descriptor Header | +----------------------------+ | System Board Status | +----------------------------+ | Domain Information | +----------------------------+ | System Board Descriptor | +----------------------------+ The details of SRAM format are out of scope of this document. It has been described in Appendix A for reference only. 3 HARDWARE DESCRIPTOR TABLE For OPL systems, the Hardware Descriptor Table is based on the following system defined parameters: Number of System Boards per Domain (SBS_PER_DOMAIN) 32 Number of Strands per Physical Core (STRANDS_PER_CORE) 4 Number of Physical Cores per CPU Chip (CORES_PER_CPU_CHIP) 4 Number of CPU Chips per CMU (CPU_CHIPS_PER_CMU) 4 Number of System Controllers per CMU (SCS_PER_CMU) 4 Number of DIMMs per CMU (DIMMS_PER_CMU) 32 Number of IOCs per IOU (IOCS_PER_IOU) 2 Number of Channels per IOC (CHANNELS_PER_IOC) 2 Number of Leaves per IOC Channel (LEAVES_PER_CHANNEL) 2 Number of IOC Channels per System Board (PCI_CHANNELS_PER_SB) 4 Number of IO Boats per IOU (IO_BOATS_PER_IOU) 6 The Hardware Descriptor on each LSB consists of the following information: (a) Hardware Descriptor Header The Hardware Descriptor Header defines the header of the hardware descriptor structure. It contains the magic number, structure revision number and offsets to the other structures in the Hardware Descriptor table. All the LSBs in the domain must contain identical Hardware Descriptor Header and XSCF ensures the consistency among all the LSBs. See section 3.2 for details. (b) System Board Status The System Board Status structure contains the status of all the system boards in the domain. It indicates the system board presence or absence status as well as the system board diagnosis status for all the LSBs that make up a domain. This information is common to all the LSBs in a domain and XSCF ensures the consistency among all the LSBs. See section 3.3 for details. (c) Domain Information Domain Information structure contains the information specific to the domain. Information like host id, model information, MAC address, system banner, platform/root name, etc. is contained in this data structure. This information is common to all the LSBs in a domain and XSCF ensures the consistency among all the LSBs. See section 3.4 for details. (d) System Board Descriptor System Board Descriptor contains the status & information of all the components that make up an LSB. This includes the information on the Processors (CMP, CORE, Strand), Memory/DIMMs, SC, MAC, Oberon Channel (PCI-CH), CMU Channel (CMU-CH), and devices beyond PCI-CH and CMU-CH. Each LSB contains information specific to its own components. See section 3.5 for details. Different components of the Hardware Descriptor are explained in the following sections. 3.1 COMMON PARAMETERS FOR HARDWARE DESCRIPTOR TABLE 3.1.1 COMPONENT STATUS Each component represented in the Hardware Descriptor Table has the device operating status. Following is the definition of the status field with the list of possible status values. The component status is defined as: typedef uint32_t hwdesc_stat_t; Possible values for hwdesc_stat_t are : #define HWDESC_STAT_UNKNOWN 0x0000 /* No status yet */ #define HWDESC_STAT_PRESENT 0x0001 /* Present */ #define HWDESC_STAT_MISS 0x0002 /* Missing */ #define HWDESC_STAT_MISCONFIG 0x0003 /* Misconfigured */ #define HWDESC_STAT_PASS 0x0004 /* Ok */ #define HWDESC_STAT_FAIL 0x0080 /* Failed by XSCF */ #define HWDESC_STAT_FAIL_OBP 0x0081 /* Failed by POST/OBP */ #define HWDESC_STAT_FAIL_OS 0x0082 /* Failed by OS */ #define HWDESC_MASK_FAIL 0x0080 /* Failed */ #define HWDESC_MASK_NOT_USED 0x8000 /* Component not in use */ /* even if it is present */ 3.1.2 CHECKSUM CALCULATION All the information in the Hardware Descriptor table is protected by Checksum. Following is the algorithm used for checksum calculation: 4-byte sum of data from the start of the structure to the end of structure excluding the check_sum field itself. void calc_checksum (struct_type structure) { uint32_t *p; uint32_t sum = 0; for (p = (uint32_t *) &structure; p < &structure.check_sum; p++) { sum += *p; } structure.check_sum = sum; } Any SW component modifying the hardware descriptor data need to make sure that the checksum is recalculated after the modification. 3.1.3 HARDWARE DESCRIPTOR VERSIONING The hardware descriptor structure version is controlled by a set of major and minor version numbers. Both major and minor version numbers are 16-bit quantity (defined in section 3.2.1). The minor version number is incremented for backward compatible changes in the hardware descriptor table structures. Such changes retain the offsets of the fields and substructures as defined by previous minor numbers, within the same major number. Thus, a consumer that understands can work reliably with the hardware descriptor structure with version , where x is greater than 0. The consumer can function reliably without any software upgrades for any minor version number change. The major version number is incremented for the changes to the hardware descriptor structure that are incompatible with the previous version. Any change that cause a shift in the offset of structure field(s) and/or substructure(s) makes the structure incompatible with the previous version. Such changes will require update of entire software stack on both domain and SCF side in order for the domain to function reliably. If consumer detects an unsupported major version, it should not attepmt to interpret the structure contents. When the major number changes the minor number will reset to 0. The offset of the structure defining the hardware descriptor version (as defined in section 3.2.1) within the hardware descriptor structure, should never change. If the format of the structure defined in section 3.2.1 needs to be changed, then it must be done in a backward compatible manner. Updates to hardware descriptor structure are expected to be very rare during the lifetime of the OPL project. Changes, if any, are expected to be minor and backward compatible. Changes that are not backward compatible are not expected to occur during the project's lifetime. The following defines how versioning is handled by the consumers of the hardware descriptor table. If the hardware descriptor table has major and minor number set to X.Y (X=major version and Y=minor version) while the domain software supports version A.B, then : If X<>A (major version numbers do not match), the interface is incompatible. The consumer should not consume the data in hardware descriptor table. An implementation may chose to shutdown the domain because system cannot function reliably unless software upgrades are made before the domain can be restarted. If X=A, (major version numbers match), If Y=B (minor version numbers match), the interface is fully compatible If YB (minor number of the consumer is lower than the minor version in hardware descriptor table), the domain can assume that it can operate compatibly with version Y because changes to minor version number are defined to be compatible with prior versions. The consumer may chose to emit a warning message to notify the difference in minor version number. 3.2 HARDWARE DESCRIPTOR HEADER The Hardware Descriptor Header (descriptor_header_t) is defined as follows: typedef struct { uint32_t magic; /* Magic code */ hwdesc_version_t version; /* Major & minor version */ uint8_t domain_id; /* Domain Identifier */ char fill[3]; /* Filler */ uint32_t sb_status_offset; /* Offset to sb_status_t */ /* from the begining of */ /* desciptor header */ uint32_t domain_information_offset; /* Offset to domain_in- */ /* formation_t from the */ /* beginning of desciptor*/ /* header */ uint32_t sb_descriptor_offset; /* Offset to hwdesc_sb_t */ /* from the beginning of */ /* desciptor header */ uint32_t spare[9]; /* For future use */ uint32_t check_sum; /* Checksum of */ /* descriptor_header_t */ } descriptor_header_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= uint32_t magic Magic code for HW descriptor Value 0x48574445 ("HWDE") hwdesc_version_t version Major & minor version number for hardware descrioptor table (section 3.2.1) uint8_t domain_id Domain Identifier. Columbus2 system can have upto 24 domains so domain id can be 0 - 23. uint32_t sb_status_offset Offset to sb_status_t struct from the begining of descriptor header uint32_t domain_information_offset Offset to domain_information_t struct from the begining of descriptor header uint32_t sb_descriptor_offset Offset to hwdesc_sb_t struct from the begining of descriptor header uint32_t check_sum Checksum of descriptor_header_t (section 3.1.2) ============================================================================ 3.2.1 VERSION INFORMATION The Hardware Descriptor Version (hwdesc_version) is defined as follows: typedef struct { /* HWD version info */ uint16_t major; /* Major version */ uint16_t minor; /* Minor version */ } hwdesc_version_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= uint16_t major Major version number for entire HWD structure. It is changed whenever the structure is changed in incompatible manner where SW backward compatibility cannot be maintained. uint16_t minor Minor version number for entire HWD structure. It is changed when there are small updates to the structure and SW backward compatibility can be maintained. (see section 3.1.3 for details) ============================================================================ 3.3 SYSTEM BOARDS STATUS The status of all the System Boards (SB) in the domain is defined in sb_status_t structure as follows: typedef struct { hwdesc_stat_t status[SBS_PER_DOMAIN]; /* Status of all SBs */ uint8_t psb_number[SBS_PER_DOMAIN]; /* PSB# of all SBs */ uint32_t spare[7]; /* For future use */ uint32_t check_sum; /* Checksum of sb_status_t */ } sb_status_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t[] status[SBS_PER_DOMAIN] Status of all the system boards present in the domain. It can be one of the following values: HWDESC_STAT_PASS HWDESC_STAT_PRESENT HWDESC_STAT_MISS HWDESC_STAT_FAIL uint8_t psb_number[SBS_PER_DOMAIN] PSB number of all the system boards present in the domain. uint32_t check_sum Checksum of sb_status_t (section 3.1.2) ============================================================================ 3.4 DOMAIN INFORMATION The Domain Information structure (domain_information_t) is defined as follows: typedef struct { uint32_t reset_factor; /* Reset reason for the domain */ uint32_t host_id; /* Domain unique id */ uint64_t system_frequency; /* Hz */ uint64_t stick_frequency; /* Hz */ uint32_t scf_command_timeout; /* Second */ uint32_t model_information; /* FF1/2 DC1/2/3 Ikkaku */ uint8_t mac_address[6]; /* 6 bytes of MAC address */ uint8_t fill1[10] /* Filler */ uint8_t dr_status; /* 0 = DR Capable, other = no DR */ uint8_t fill2[7]; /* Filler */ uint8_t configuration_policy; /* Degrade factor */ uint8_t diag_level; /* Diagnostics level */ uint8_t boot_mode; /* Boot control */ uint8_t sparc64vi_compatible_mode /* 0x80 = SPARC64-VI mode */ /* Other = Auto mode */ uint8_t spare1[4]; /* For future use */ int64_t cpu_start_time; /* Seconds since 1970-01-01 */ /* 00:00:00 UTC */ char banner_name[64]; /* System banner string */ char platform_token[64]; /* Platform name */ uint32_t floating_board_bitmap; /* Floating boards bitmap */ char chassis_sn[16]; /* Chassis serial number */ uint32_t brand_control; /* Domain brand control */ uint32_t spare2[7] /* For future use */ uint32_t check_sum; /* Checksum of */ /* domain_information_t */ } domain_information_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= uint32_t reset_factor Reason for domain reset 0x8000.0000 - AC_POR 0x4000.0000 - SOFT_POR 0x2000.0000 - SOFT_XIR 0x1000.0000 - B_POR 0x0800.0000 - B_XIR 0x0200.0000 - FATAL 0x0002.0000 - DR_POR 0x0001.0000 - DR_RTI0 (new board) 0x0000.8000 - DR_RTI1 (change) uint32_t host_id Id of the current host. This is the same value as printed by /usr/bin/hostid command uint64_t system_frequency System Frequency in Hertz uint64_t stick_frequency Stick Frequency in Hertz uint32_t scf_command_timeout SCF Interface timeout in seconds uint32_t model_information System model FF1/FF2/DC1/DC2/DC3/ Ikkaku. 1:FF1, 2:FF2, 3:DC1, 4:DC2, 5:DC3 6:Ikkaku uint8_t[] mac_address[6] System MAC address uint8_t dr_status Indicates if domain supports DR 0:DR Capable, Other:Not DR capable uint8_t configuration_policy Degrade factor. Indicates how a failed component should be degraded. Based on the setting, the failed component could be degraded, or the entire board can be degraded, or the entire system could be degraded. Values 0x00:off, 0x20:component, 0x40:board, 0x80:system uint8_t diag_level Diagnostics level for POST. Values 0x00:off, 0x20:min, 0x40:max uint8_t boot_mode Boot control direction set by XSCF. 0x10 : Enter POST monitor after POST completes. 0x20 : Invoke POST Test Program. 0x00, Other : Enter OpenBoot after POST is completed. Options 0x10 & 0x20 are for Sun/FJ internal/field use only. uint8_t sparc64vi_compatible_mode 0x80 = SPARC64-VI mode. Force the domain to run in SPARC64-VI mode. Other = Auto mode. Domain execution mode is determined by the CPU configuration in the domain. int64_t cpu_start_time Time when XSCF started the CPUs. In seconds since 1970-01-01 0:00 UTC char[] banner_name[64] System banner name char[] platform_token[64] System platform name uint32_t floating_board_bitmap Bitmap list for the floating boards in the domain. Bit_N = 1 means SB_N is floating Bit 0:SB0 floating? Bit 1:SB1 floating? ... char[] chassis_sn[16] Chassis serial number as stored in the panel device. uint32_t brand_control A bitmap indicating the functions installed on the OPL machine. The value can vary depending upon the machine branding (Sun/Fujitsu/OEM) 0x00000001 : SRS Installed 0x00000002 : REMCS installed 0x00000004 : SunMC installed 0x00000008 : Dimm Install 0x00000010 : Domain initiated DR 0x00008000 : RCI support uint32_t check_sum Checksum of domain_information_t (section 3.1.2) ============================================================================ 3.5 SYSTEM BOARD DESCRIPTOR Information related to the System Board is as follows: typedef struct { /* SB */ hwdesc_stat_t status; /* Status of this SB */ uint8_t sb_mode; /* PSB or XSB */ uint8_t psb_number; /* PSB# to which this SB belongs */ uint8_t fill1[10]; /* Filler */ /* CMU */ hwdesc_cmu_t cmu; /* CMU details */ /* PCI CH */ hwdesc_pci_ch_t pci_ch[PCI_CHANNELS_PER_SB];/* PCI_CH details */ uint32_t spare[31]; /* For future use */ uint32_t check_sum; /* Checksum for hwdesc_sb_t */ } hwdesc_sb_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of this system board uint8_t sb_mode System board mode PSB or XSB 0: PSB mode 1: XSB mode uint8_t psb_number PSB number where this SB is mounted Value 0 - f (upto 16 PSBs) hwdesc_cmu_t cmu Information on the CMU (section 3.5.4) hwdesc_pci_ch_t[] pci_ch[PCI_CHANNELS_PER_SB] Information on PCI Channel (section 3.5.6) uint32_t check_sum Checksum of hwdesc_sb_t structure (section 3.1.2) ============================================================================ All the structures referred to by system board information structure are defined in the following sub-sections. 3.5.1 CPU STRAND (VIRTUAL CPU) INFORMATION The CPU Strand information structure (hwdesc_strand_t) is defined as follows: typedef struct { hwdesc_stat_t status; /* Strand status */ char component_name[32]; /* Strand name string */ uint16_t cpu_id; /* CPUID of virtual cpu/strand */ uint16_t fill; /* Filler */ uint32_t spare[6]; /* For future use */ } hwdesc_strand_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of this strand. Can be one of the following: HWDESC_STAT_PASS HWDESC_STAT_PRESENT HWDESC_STAT_MISS HWDESC_STAT_FAIL char[] component_name[32] Component name to identify strand uint16_t cpu_id CPU ID for this strand. Refer to Jupiter Bus Bindings FWARC/2005/076 [2] for the format of cpu_id. ============================================================================ 3.5.2 CPU PHYSICAL CORE INFORMATION The CPU Physical Core information structure (hwdesc_core_t) is defined as follows: typedef struct { hwdesc_stat_t status; /* Core status */ char component_name[32]; /* Core name string */ uint32_t fill1; /* Filler */ uint64_t frequency; /* Hz */ uint64_t config; /* jupiter bus config reg */ uint64_t version; /* version register */ uint16_t manufacturer; /* Manufacturer Id */ uint16_t implementation; /* Implementation Id */ uint8_t mask; /* Mask set revision */ uint8_t fill2[3]; /* Filler */ uint32_t l1_icache_size; /* I$ size */ uint16_t l1_icache_line_size;/* I$ line size */ uint16_t l1_icache_associativity; /* I$ associativity */ uint32_t number_of_itlb_entries; /* #iTLB entries */ uint32_t l1_dcache_size; /* D$ size */ uint16_t l1_dcache_line_size; /* D$ line size */ uint16_t l1_dcache_associativity; /* D$ associativity */ uint32_t number_of_dtlb_entries; /* #dTLB entries */ uint32_t spare1[4]; /* For future use */ uint32_t l2_cache_size; /* L2$ size */ uint16_t l2_cache_line_size; /* L2$ line size */ uint16_t l2_cache_associativity; /* L2$ associativity */ uint32_t l2_cache_sharing; /* bitmap: bit0=core0, */ /* bit1=core1, ... */ uint32_t spare2[5]; /* For future use */ hwdesc_strand_t strand[STRANDS_PER_CORE];/* CPU strands info */ uint32_t spare3[4]; /* For future use */ } hwdesc_core_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of this Physical Core. Can be one of the following: HWDESC_STAT_PASS HWDESC_STAT_PRESENT HWDESC_STAT_MISS HWDESC_STAT_FAIL char[] component_name[32] Component name to identify Core uint64_t frequency CPU Speed in Hz uint64_t config Jupiter bus config register value uint64_t version Processor Version register (VER) uint16_t manufacturer VER.manuf field uint16_t implementation VER.impl field uint8_t mask VER.mask field uint32_t l1_icache_size I-Cache size in bytes uint16_t l1_icache_line_size I-Cache line size in bytes uint16_t l1_icache_associativity I-Cache associativity uint32_t number_of_itlb_entries Number of I-TLB entries uint32_t l1_dcache_size D-Cache size in bytes uint16_t l1_dcache_line_size D-Cache line size in bytes uint16_t l1_dcache_associativity D-Cache associativity uint32_t number_of_dtlb_entries Number of D-TLB entries uint32_t l2_cache_size Level-2 Cache size in bytes uint16_t l2_cache_line_size Level-2 Cache line size in bytes uint16_t l2_cache_associativity Level-2 Cache associativity uint32_t l2_cache_sharing L2 Cache sharing between the Cores Bitmap: bit0=core0, bit1=core1,... hwdesc_strand_t[] strand[STRANDS_PER_CORE] Information about each strand in this Cores. (section 3.5.1) ============================================================================ 3.5.3 PROCESSOR (CPU Chip) INFORMATION The Processor (CPU Chip) information structure (hwdesc_cpu_chip_t) is defined as follows: typedef struct { hwdesc_stat_t status; /* CMP Chip status */ char component_name[32]; /* Processor name string */ char fru_name[32]; /* example: "CPU#x" */ char compatible[32]; /* example: "FJSV,SPARC64-VI" */ uint16_t port_id; /* logical id */ uint16_t fill; /* Filler */ uint32_t spare1[6]; /* For future use */ hwdesc_core_t core[CORES_PER_CPU_CHIP]; /* Physical cores info */ uint32_t spare2[4]; /* For future use */ } hwdesc_cpu_chip_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of this Processor (CPU Chip). Can be be one of the following: HWDESC_STAT_PASS HWDESC_STAT_PRESENT HWDESC_STAT_MISS HWDESC_STAT_FAIL char[] component_name[32] Component name to identify this chip Example "CPU#X" char[] fru_name[32] FRUid name assigned to this chip Example "CPU#X" char[] compatible[32] Compatible name string Value "FJSV,SPARC64-VI" for Olympus-C Value "FJSV,SPARC64-VII" for Jupiter uint16_t port_id Jupiter bus Port ID Refer to Jupiter Bus Bindings FWARC/2005/076 [2] for the format of port_id. hwdesc_core_t[] core[CORES_PER_CPU_CHIP] Information about each Core in this CPU chip (section 3.5.2) ============================================================================ 3.5.4 CPU & MEMORY UNIT (CMU) INFORMATION The information related to a CMU is represented as define below: typedef struct { char component_name[32]; /* Component name string */ char fru_name[32]; /* FRU name string */ hwdesc_cpu_chip_t cpu_chip[CPU_CHIPS_PER_CMU]; /* CPU Chips info */ hwdesc_sc_t sc[SCS_PER_CMU]; /* SC chips info */ hwdesc_memory_t memory; /* Memory info */ hwdesc_cmuch_t ch; /* CMU-Ch info */ uint32_t spare[32] /* For future use */ } hwdesc_cmu_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= char[] component_name[32] Component name to idenfity this CMU Example: "CxS0y" char[] fru_name[32] FRU name assigned to this CMU Example: "Cabinet#x-CMU#y" hwdesc_cpu_chip_t[] cpu_chip[CPU_CHIPS_PER_CMU] Information about each CPU chip on the CMU. (section 3.5.3) hwdesc_sc_t[] sc[SCS_PER_CMU] Information about each SC chip on the CMU (section 3.5.4.1) hwdesc_memory_t memory Information about the installed memory on the CMU (section 3.5.4.2) hwdesc_cmuch_t ch Information about the CMU-CH installed on the CMU (section 3.5.4.3) ============================================================================ 3.5.4.1 SC_CHIP INFORMATION The information about each SC chip is represented as defined below: typedef struct { hwdesc_stat_t status; /* Status of SC */ uint32_t fill; /* Filler */ uint64_t register_address; /* SC register address */ } hwdesc_sc_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of SC. Can be be one of the following: HWDESC_STAT_PASS HWDESC_STAT_PRESENT HWDESC_STAT_FAIL uint64_t register_address Starting physical address of SC registers. ============================================================================ 3.5.4.2 MEMORY INFORMATION The information about the memory sub-system is defined below: typedef struct { uint64_t start_address; /* Memory space for this SB */ uint64_t size; /* CAB/Memory size */ hwdesc_bank_t bank[8]; /* Info about memory banks */ uint8_t mirror_mode; /* Memory mirroring mode */ uint8_t division_mode; /* Memory configuration */ uint8_t piece_number; /* Memory piece# connected */ /* to this SB */ uint8_t cs_interleave; /* 0:not cs interleaved, */ /* 1:cs interleaved */ uint32_t fill[3]; /* Filler */ uint8_t available_bitmap[512];/* Available partial mem */ uint8_t degrade_bitmap[16384];/* Degraded partial mem */ hwdesc_chunk_t chunk[8]; /* Info about memory chunks */ hwdesc_dimm_t dimm[DIMMS_PER_CMU];/* Info about each memory dimm */ hwdesc_cs_t cs[2]; /* Info about CS pair */ } hwdesc_memory_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= uint64_t start_address Starting physical address of LSB memory space (start addr of CAB) uint64_t size CAB size of this SB hwdesc_bank_t[] bank[8] Info about memory banks (section 3.5.4.2.1) uint8_t mirror_mode Memory mirroring mode 0: Not memory mirror mode 1: Memory mirror mode uint8_t division_mode Memory configuration - number of segments in memory (1, 2 or 4) 1: 1 divided mode 2: 2 divided mode 4: 4 divided mode In XSB mode, division mode is 4, In PSB mode, it can be 1, 2, or 4. uint8_t piece_number Number of memory piece assigned to this LSB (0-3). Shows the memory slot group used. For FF systems: Division mode 4 Piece# 0 Bank# 0,1 Piece# 1 Bank# 2,3 Piece# 2 Bank# 4,5 Piece# 3 Bank# 6,7 Division mode 2 Piece# 0 Bank# 0,1,2,3 Piece# 1 Bank# 4,5,6,7 Division mode 1 Piece# 0 Bank# 0,1,2,3,4,5,6,7 For DC systems: Division mode 4 Piece# 0 Bank# 0,4 Piece# 1 Bank# 1,5 Piece# 2 Bank# 2,6 Piece# 3 Bank# 3,7 Division mode 2 Piece# 0 Bank# 0,2,4,6 Piece# 1 Bank# 1,3,5,7 Division mode 1 Piece# 0 Bank# 0,1,2,3,4,5,6,7 uint8_t cs_interleave 0:not cs interleave, 1:cs interleave uint8_t[] available_bitmap[512] Available memory bitmap. Info on partial memory areas in Physical Address that are available or that show partial degeneration. Each bit in the available_bitmap represents a 64MB block of memory. Bit value of 1 means available area, a value of 0 means degraded or not populated area. This bitmap shows the physical memory space. uint8_t[] degrade_bitmap[16384] Degraded memory bitmap. Info on partial memory degrade in DIMM address. Bit value of 1 means degraded area, a value of 0 means available or not populated area. The bitmap shows the Memory Access Controller address and is divided by the unit of memory interleave that is more detailed compared to available_bitmap. hwdesc_chunk_t[] chunk[8] Info about memory chunks. A chunk is a contiguous memory region. Info for upto eight chunks is maintained. (section 3.5.4.2.2) hwdesc_dimm_t dimm[DIMMS_PER_CMU] Info about the memory dimms (section 3.5.4.2.3) hwdesc_cs_t cs[2] Info about the CS pairs (section 3.5.4.2.4) ============================================================================ 3.5.4.2.1 MEMORY BANK INFORMATION The information about the memory bank is defined as follows: typedef struct { hwdesc_stat_t status; /* Bank status */ hwdesc_stat_t cs_status[2]; /* DIMM pair status */ uint32_t fill1; /* Filler */ uint64_t register_address; /* Address of memory */ /* patrol related regs */ uint8_t mac_ocd; /* Calibrated MAC_OCD val */ uint8_t fill2[3]; /* Filler */ uint8_t dimm_ocd[4][2]; /* Calibrated DIMM_OCD val */ uint32_t tune; /* Calibrated DQS timing */ uint32_t spare[2]; /* For future use */ } hwdesc_bank_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of this memory bank. Can be be one of the following: HWDESC_STAT_PASS HWDESC_STAT_PRESENT HWDESC_STAT_MISS HWDESC_STAT_FAIL hwdesc_stat_t[] cs_status[2] Status of DIMM pair in the same CS. (status of bank CS controls). Can be be one of the following: HWDESC_STAT_PRESENT: DIMMs of same type & size present in pairs HWDESC_STAT_MISS: Both the DIMMs in the DIMM pair missing HWDESC_STAT_MISCONFIG: Condition other than above. uint64_t register_address Starting physical address of MAC registers for the memory bank. uint8_t mac_ocd POST calibrated value for MAC OCD fields in MAC register. Used to initialize MAC. uint8_t[][] dimm_ocd[4][2] POST calibrated value for DIMM OCD fields in MAC registers. Used to initialize MAC. uint32_t tune POST calibrated value for DQS timing. Used to initialize MAC. ============================================================================ 3.5.4.2.2 MEMORY CHUNK INFORMATION The information about the memory chunk is defined as follows: typedef struct { uint64_t start_address; /* Chunk start address */ uint64_t size; /* Chunk size */ } hwdesc_chunk_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= uint64_t start_address Start address of the memory chunk. Address should be 64MB aligned. Information of upto 8 memory chunks is kept. In case more then 8 chunks exist in the system, only 8 biggest chunks are represented in the HWD. uint64_t size Size of this memory chunk. Min value of size can be 0 (0 => non-existent chunk), max value can be 265GB. ============================================================================ 3.5.4.2.3 MEMORY DIMM INFORMATION The information about memory DIMMs is defined as follows: typedef struct { hwdesc_stat_t status; /* DIMM status */ uint32_t fill1; /* Filler */ uint64_t capacity; /* in bytes */ uint64_t available_capacity; /* in bytes */ uint8_t rank; /* 1: 1 rank DIMM */ /* 2: 2 rank DIMM */ uint8_t fill2[7]; /* Filler */ char component_name[32]; /* "MEM#xyz" */ char fru_name[32]; /* "MEM#xyz" */ } hwdesc_dimm_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of this DIMM Can be be one of the following: HWDESC_STAT_PASS HWDESC_STAT_PRESENT HWDESC_STAT_MISS HWDESC_STAT_FAIL uint64_t capacity Size of DIMM in bytes uint64_t available_capacity Available memory on the DIMM in bytes uint8_t rank Type of DIMM module. 1: 1 rank, 2: 2 rank char[] component_name[32] Component name assigned to this DIMM char[] fru_name[32] FRUid name assigned to this DIMM ============================================================================ 3.5.4.2.4 MEMORY CS_PAIR INFORMATION The information about memory CS pairs is defined as follows: typedef struct { hwdesc_stat_t status; /* CS Status */ uint8_t number_of_dimms; /* Number of dimms */ uint8_t fill[3] /* Filler */ uint64_t available_capacity; /* CS total available */ /* in bytes */ uint64_t dimm_capacity; /* One dimm capacity */ /* in bytes */ uint8_t dimm_badd[8]; /* DIMM_BADD value for */ /* DIMM initial setting */ uint16_t dimm_add[8]; /* DIMM_ADD value for */ /* DIMM initial setting */ uint8_t pa_mac_conversion_table[64]; /* PA <-> MAC address */ } hwdesc_cs_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of the memory group. possible values are: HWDESC_STAT_PRESENT: normal & present HWDESC_STAT_MISS: no DIMM present HWDESC_STAT_FAIL: other than above Following algorithm is followed: If all bank[n].cs_status[i] in the LSB are HWDESC_STAT_PRESENT, it is set to HWDESC_STAT_PRESENT. If all bank[n].cs_status[i] in the LSB are HWDESC_STAT_MISS, it is set to HWDESC_STAT_MISS. For anyother values of bank[n].cs_status[i], it is set to HWDESC_STAT_FAIL. uint8_t number_of_dimms Number of dimms in the CS. uint64_t available_capacity Available memory in CS (in bytes) uint64_t dimm_capacity Size of one DIMM used in this CS (in bytes) uint8_t[] dimm_badd[8] Values used by POST to setup memory Initial Setting register uint16_t[] dimm_add[8] Values used by POST to setup memory Initial Setting register uint8_t[] pa_mac_conversion_table[64] Information used to convert the memory Physical address to DIMM address and vice-versa. ============================================================================ 3.5.4.3 CMU CHANNEL (CMU-CH) INFORMATION The information about CMU-CH is defined as follows: typedef struct { hwdesc_stat_t status /* Status of CMU-CH */ uint16_t port_id; /* Portid of CMU-CH */ uint16_t fill; /* Filler */ char component_name[32]; /* Component name str */ hwdesc_scf_interface_t scf_interface; /* SCF Interface info */ hwdesc_serial_t serial; /* Serial port info */ hwdesc_fmem_t fmem[2]; /* Flash memory info */ } hwdesc_cmuch_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of CMU-CH Can be one of the following: HWDESC_STAT_PRESENT HWDESC_STAT_PASS HWDESC_STAT_FAIL uint16_t port_id Port ID of the CMU-CH LSB0:0x08, LSB1:0x18, .. LSB15:0xf8 Refer to Jupiter Bus Bindings FWARC/2005/076 [2] for the format of port_id. char[] component_name[32] Component name assigned to CMU-CH hwdesc_scf_interface_t scf_interface Information about SCF Interface (section 3.5.4.3.1) hwdesc_serial_t serial Information about the serial port (section 3.5.4.3.2) hwdesc_fmem_t[] fmem[2] Information about Flash memory proms (section 3.5.4.3.3) ============================================================================ 3.5.4.3.1 SCF INTERFACE INFORMATION The information about the SCF Interface is defined as follows: typedef struct { hwdesc_stat_t status; /* SCF interface status */ char component_name[32]; /* "SCFI#z" */ } hwdesc_scf_interface_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of SCF interface Can be one of the following: HWDESC_STAT_PRESENT HWDESC_STAT_PASS HWDESC_STAT_FAIL char[] component_name[32] Component name assigned to this SCF Example: "SCFI#z" ============================================================================ 3.5.4.3.2 SERIAL PORT INFORMATION The information about the Serial port (tty) is defined as follows: typedef struct { hwdesc_stat_t status; /* Status of tty */ char component_name[32]; /* "TTY#z" */ } hwdesc_serial_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of Serial port Can be one of the following: HWDESC_STAT_PRESENT HWDESC_STAT_PASS HWDESC_STAT_FAIL char[] component_name[32] Component name assigned to this Serial port. Example: "TTY#z" ============================================================================ 3.5.4.3.3 FLASH MEMORY INFORMATION The information about the Flash memory (PROM) is defined as follows: typedef struct { hwdesc_stat_t status; /* Status of flash */ char component_name[32]; /* Component name str */ uint8_t used; /* <>0: fmem is used */ uint8_t fill[3]; /* Filler */ hwdesc_fmem_version_t version; /* Firmware version info */ uint32_t spare; /* For future use */ } hwdesc_fmem_t; /* Flash memory */ ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of Flash bank Can be one of the following: HWDESC_STAT_PRESENT HWDESC_STAT_PASS HWDESC_STAT_FAIL char[] component_name[32] Component name assigned to the Flash bank uint8_t used Flash bank used or not 0: FMEM bank not used 1: FMEM bank in use hwdesc_fmem_version_t version Firmware version infotmation (section 3.5.4.3.3.1) ============================================================================ 3.5.4.3.3.1 FIRMWARE VERSION INFORMATION The information about the Firmware version residing in the Flash memory is defined as follows: typedef struct { uint8_t major; /* Firmware major ver# */ uint8_t minor; /* Firmware minor ver# */ uint8_t local; /* Firmware local ver# */ uint8_t fill; /* Filler */ } hwdesc_fmem_version_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= uint8_t major Firmware major version uint8_t minor Firmware minor version uint8_t local Firmware local version ============================================================================ 3.5.5 IO BOAT INFORMATION 3.5.5.1 IO BOAT SLOT INFORMATION An IO slot is defined as follows: typedef struct { hwdesc_stat_t status; /* Status of IO slot */ char slot_name[16]; /* IO slot name */ } hwdesc_slot_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of the IO slot char[] slot_name[16] IO slot name ============================================================================ 3.5.5.2 IO BOAT DETAILS The information related to the IO Boat is defined below: typedef struct { hwdesc_stat_t status; char component_name[32]; /* Component name string */ char fru_name[32]; /* FRU name string */ uint32_t type; /* PCI-X or PCI Express */ uint64_t io_box_information; /* IObox# where IO boat is */ /* mounted */ hwdesc_stat_t switch_status[3]; /* Status of PCIE switches in */ /* IO boat */ hwdesc_stat_t bridge_status[3]; /* Status of PCIX bridges in */ /* IO boat */ hwdesc_slot_t slot[6]; /* IO slot information */ uint32_t spare[8] /* For future use */ } hwdesc_io_boat_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of the IO Boat char[] component_name[32] Component name assigned to IOBoat char[] fru_name[32] FRU name assigned to IOBoat uint32_t type IOBoat type (PCIE or PCIX) 1: PCIX slot type 2: PCIE slot type uint64_t io_box_information IO Box number where IO boat is mounted. Location of IOBox. hwdesc_stat_t[] switch_status[3] Status of the PCIE Switches in the IOBoat. Only switch_status[0] is used for PCIX type IOBoat. hwdesc_stat_t[] bridge_status[3] Status of the PCIE-PCIX bridges in the IOBoat. Only used for PCIX type IOBoat. hwdesc_slot_t[] slot[6] IO slots information (section 3.5.5.1) ============================================================================ 3.5.6 PCI CHANNEL INFORMATION (PCI-CH / IO Channel in IOC or Oberon) 3.5.6.1 IO UNIT PCIE SLOT INFORMATION A PCI Express slot on an IO Unit is defined as follows: typedef struct { uint32_t type; /* 0:empty, 1:Card, 2:IOBoat */ hwdesc_slot_t slot; /* Slot info */ hwdesc_io_boat_t io_boat; /* IO Boat info if type=IOBoat */ } hwdesc_iou_slot_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= uint32_t type Type of device in the PCIE slot 0 : Slot is empty 1 : PCIE card plugged in 2 : IOBoat plugged in hwdesc_slot_t slot PCIE slot related info (section 3.5.5.1) hwdesc_io_boat_t io_boat IO Boat information if 'type=2' (section 3.5.5.2) ============================================================================ 3.5.6.2 PCI CHANNEL DETAILS The PCI Channel (PCI_CH) information is as follows: typedef struct { hwdesc_stat_t status; /* Status of PCI Channel */ char component_name[32]; /* Component name string */ char fru_name[32]; /* FRU name string */ uint8_t fill[12]; /* Filler */ hwdesc_leaf_t leaf[LEAVES_PER_CHANNEL]; /* Info about PCI CH leaf */ } hwdesc_pci_ch_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of PCI Channel Can be one of the following: HWDESC_STAT_PRESENT HWDESC_STAT_PASS HWDESC_STAT_FAIL char[] component_name[32] Component name assigned to this IOU char[] fru_name[32] FRU name assigned to this IOU hwdesc_leaf_t[] leaf[LEAVES_PER_CHANNEL] Info about PCI Channel leaves (section 3.5.6.2.1) ============================================================================ 3.5.6.2.1 PCI CHANNEL LEAF INFORMATION The information about the PCI_CH leaf is defined as follows: typedef struct { hwdesc_stat_t status; /* Status of PCI Leaf */ uint16_t port_id; /* Portid (Logical leaf id) */ /* assigned to the PCI leaf */ uint8_t fill[6]; /* Filler */ uint32_t type; /* 1:FF onboard, 2:IOUA, 3:slot */ /* 4:Ikkaku leaf A, 5:Ikkaku leaf B */ union { /* Union based on type field */ hwdesc_ff_onboard_t ff_onboard; /* Onboard IO FF systems */ hwdesc_ioua_t ioua; /* IO unit DC systems */ hwdesc_iou_slot_desc_t slot; /* PCIE slot */ hwdesc_ikk_leafa_t ikk_leafa; /* Ikkaku leaf A */ hwdesc_ikk_leafb_t ikk_leafb; /* Ikkaku leaf B */ uint8_t spare[448]; /* 448 byes size of union*/ } u; uint64_t cfgio_offset; /* Config space offset */ uint64_t cfgio_size; /* Config space size */ uint64_t mem32_offset; /* 32bit memory space offset */ uint64_t mem32_size; /* 32bit memory space size */ uint64_t mem64_offset; /* 64bit memory space offset */ uint64_t mem64_size; /* 64bit memory space size */ } hwdesc_leaf_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of PCI Channel leaf Can be one of the following: HWDESC_STAT_PRESENT HWDESC_STAT_PASS HWDESC_STAT_FAIL uint16_t port_id Portid (Logical leaf id) Refer to Jupiter Bus Bindings FWARC/2005/076 [2] for the format of port_id. uint32_t type Type of device connected to the leaf. 1: FF Onboard IO 2: DC IO Unit 3: PCIE slot 4: Ikkaku Leaf A 5: Ikkaku Leaf B Based on this field the data in the union is used. union u Union of Onboard IO for FF system (section 3.5.6.2.1.1.), IO Unit for DC system (section 3.5.6.2.1.2), PCIE slot information (section 3.5.6.2.1.3), Ikkaku Onboard IO leaf A (section 3.5.6.2.1.4), and Ikkaku Onboard IO leaf B (section 3.5.6.2.1.5). Max size of the union is 448 bytes. Union is interpreted as per the value of 'type' field. uint64_t cfgio_offset Config Space offset uint64_t cfgio_size Config Space size uint64_t mem32_offset 32-bit memory offset uint64_t mem32_size 32-bit memory size uint64_t mem64_offset 64-bit memory offset uint64_t mem64_size 64-bit memory size ============================================================================ 3.5.6.2.1.1 ONBOARD IO (FF SYSTEM) INFORMATION The information about the FF System Onboard IO is defined as follows: typedef struct { hwdesc_stat_t switch_status; /* PCIE switch stat */ uint8_t fill[64]; /* Filler */ hwdesc_stat_t bridge_status; /* PCIX bridge stat */ hwdesc_stat_t sas_status; /* SAS status */ hwdesc_stat_t gbe_status; /* GbE status */ hwdesc_iou_slot_t slot; /* PCIE slot info */ hwdesc_slot_t xslot; /* PCIX slot info */ } hwdesc_ff_onboard_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t switch_status Status of PCIE Switch on the IOU. Set when the leaf is connected to a PCIE switch. hwdesc_stat_t bridge_status Status of PCIX bridge on the IOU. Set when the leaf is connected to a PCIE-PCIX bridge. Also set when the leaf is connected to a PCIE switch and the switch is connected to PCIE-PCIX bridge. hwdesc_stat_t sas_status Status of SAS controller on IOU Set of the leaf that has on-board devices. hwdesc_stat_t gbe_status Status of Gb Ethernet on IOU Set of the leaf that has on-board devices. hwdesc_iou_slot_t slot PCIE slot information (section 3.5.6.1) hwdesc_slot_t xslot PCIX slot information (section 3.5.5.1) ============================================================================ 3.5.6.2.1.2 IO UNIT (DC SYSTEM) INFORMATION The information about the DC system IO Unit is defined as follows: typedef struct { hwdesc_stat_t status; /* IOUA status */ char component_name[32]; /* Component name */ char fru_name[32]; /* FRU name string */ hwdesc_stat_t bridge_status; /* PCIX bridge stat */ hwdesc_stat_t sas_status; /* SAS status */ hwdesc_stat_t gbe_status; /* GbE status */ } hwdesc_ioua_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_stat_t status Status of the IOUA char[] component_name[32] Component name of IOUA char[] fru_name[32] FRU name assigned to IOUA hwdesc_stat_t bridge_status Status of PCIX bridge on the IOU. Set when the leaf is connected to a PCIE-PCIX bridge. Also set when the leaf is connected to a PCIE switch and the switch is connected to PCIE-PCIX bridge. hwdesc_stat_t sas_status Status of SAS controller on IOU Set of the leaf that has on-board devices. hwdesc_stat_t gbe_status Status of Gb Ethernet on IOU Set of the leaf that has on-board devices. ============================================================================ 3.5.6.2.1.3 ONBOARD/IO UNIT PCIE SLOT INFORMATION The information about the PCIE slot on Onboard IO (FF) and IO Unit (DC) is defined as follows: typedef struct { uint8_t fill[80] /* Filler */ hwdesc_iou_slot_t slot; /* PCIE slot info */ } hwdesc_iou_slot_desc_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_iou_slot_t slot Information on the PCIE slot under the leaf (section 3.5.6.1) ============================================================================ 3.5.6.2.1.4 IKKAKU ONBOARD IO LEAF A ONBOARD IO INFORMATION The information about the Ikkaku onboard IO leaf A is defined as follows: typedef struct { hwdesc_stat_t switch_status; /* PCIE switch stat */ uint8_t fill[68]; /* Filler */ hwdesc_stat_t sas_status; /* SAS status */ hwdesc_stat_t gbe0_status; /* GbE#0 status */ uint8_t fill2[280]; /* Filler */ hwdesc_slot_t eslot0; /* PCIE slot info (PCI#0) */ uint8_t fill3[40]; /* Filler */ hwdesc_stat_t gbe1_status; /* GbE#1 status */ } hwdesc_ikk_leafa_t; =========================================================================== Data type Field Name Description ============== ======================== ================================ hwdesc_stat_t switch_status Status of PCIE Switch on the IOU. Set when the leaf is connected to a PCIE switch. hwdesc_stat_t sas_status Status of SAS controller on IOU Set of the leaf that has on-board devices. hwdesc_stat_t gbe0_status Status of Gb Ethernet #0 on IOU Set of the leaf that has on-board devices. hwdesc_stat_t gbe1_status Status of Gb Ethernet #1 on IOU Set of the leaf that has on-board devices. hwdesc_slot_t eslot0 IO slot information for PCI#0 (section 3.5.5.1) ============================================================================ 3.5.6.2.1.5 IKKAKU ONBOARD IO LEAF B ONBOARD IO INFORMATION The information about the Ikkaku onboard IO leaf B is defined as follows: typedef struct { uint8_t fill[80]; /* Filler */ hwdesc_slot_t eslot1; /* PCIE slot info (PCI#1) */ hwdesc_slot_t eslot2; /* PCIE slot info (PCI#2) */ hwdesc_slot_t eslot3; /* PCIE slot info (PCI#3) */ } hwdesc_ikk_leafb_t; ============================================================================ Data type Field Name Description ============== ======================== ================================= hwdesc_slot_t eslot1 IO slot information for PCI#1 (section 3.5.5.1) hwdesc_slot_t eslot2 IO slot information for PCI#2 (section 3.5.5.1) hwdesc_slot_t eslot3 IO slot information for PCI#3 ============================================================================ APPENDIX A - SRAM FORMAT Details of SRAM format are described here for refernce only. It is out of scope of the Hardware Descriptor description. The SRAM has different format as seen by SCF and Domain. A.1 SCF VIEW (SRAM as seen by SCF) +--------------------------------------------------------------------+ SRAM Module | Offset | Size | Access from SCF +--------------------------------------------------------------------+ DSCP Buffer | XSB 0 | 0x00000 | 64K | Read/Write +--------+-------------+-------+ | XSB 1 | 0x10000 | 64K | +--------+-------------+-------+ | XSB 2 | 0x20000 | 64K | +--------+-------------+-------+ | XSB 3 | 0x30000 | 64K | +--------------------------------------------------------------------+ CMD I/F Buffer | XSB 0 | 0x40000 | 64K | Read/Write +--------+-------------+-------+ | XSB 1 | 0x50000 | 64K | +--------+-------------+-------+ | XSB 2 | 0x60000 | 64K | +--------+-------------+-------+ | XSB 3 | 0x70000 | 64K | +--------------------------------------------------------------------+ Domain/SP | XSB 0 | 0x80000 | 384K | SCF configures the Interface +--------+-------------+-------+ R/W attributes Buffer | XSB 1 | 0xA0000 | 384K | as per the usage +--------+-------------+-------+ of the area. | XSB 2 | 0xC0000 | 384K | +--------+-------------+-------+ | XSB 3 | 0xE0000 | 384K | +--------------------------------------------------------------------+ A.2 DOMAIN VIEW (SRAM as seen by Domain) +--------------------------------------------------------------------+ SRAM Module | Offset | Size | Access from SCF +--------------------------------------------------------------------+ DSCP Buffer | XSB 0 | 0x00000 | 64K | Read/Write +--------------------------------------------------------------------+ CMD I/F Buffer | XSB 0 | 0x10000 | 64K | Read/Write +--------------------------------------------------------------------+ Domain/SP I/F | XSB 0 | 0x20000 | 384K | As per the usage +--------------------------------------------------------------------+ A.3 DOMAIN/SP INTERFACE BUFFER +--------------------------------------------------------------------+ Function | Offset | Size | Domain | SCF +--------------------------------------------------------------------+ Header | 0x00000 | 256 | 8K | R | RW +-----------------------------+---------+-------+ | | Reserved | 0x00100 | 7936 | | | +--------------------------------------------------------------------+ Configuration Info | 0x02000 | 4096 | 4K | RW | R(W) +--------------------------------------------------------------------+ Hardware Descriptor | 0x03000 | 36864 | 36K | RW | R(W) +--------------------------------------------------------------------+ OBP Environment | 0x0C000 | 8192 | 8K | RW | R(W) +--------------------------------------------------------------------+ CPU Signature | 0x0E000 | 8192 | 8K | RW | R +--------------------------------------------------------------------+ OBP | show-post-message | 0x10000 | 4096 | 16K | RW | R Local +--------------------+---------+-------+ | | | Reserved | 0x11000 | 4096 | | | +--------------------+---------+-------+ | | | POST Work Area | 0x12000 | 4096 | | | +--------------------+---------+-------+ | | | OBP Work Area | 0x13000 | 4096 | | | +--------------------------------------------------------------------+ Detail | POST/OBP Trace | 0x14000 | 16384 | 32K | RW | R Log/ +--------------------+---------+-------+ | | Trace | SCF Driver Trace | 0x18000 | 4096 | | | +--------------------+---------+-------+ | | | OBP Detail Log | 0x19000 | 8192 | | | +--------------------+---------+-------+ | | | Reserved | 0x1B000 | 4096 | | | +--------------------------------------------------------------------+ Red State Log | 0x1C000 | 262144| 256K| RW | R 8K/Strand * 32 Strands | | | | | +--------------------------------------------------------------------+ Reserved | 0x5C000 | 16384 | 16K | +--------------------------------------------------------------------+