#pragma ident "@(#)pci-e.binding.txt 1.6 10/02/19 SMI" Copyright 2010 Sun Microsystems Inc. All rights reserved. Use is subject to license terms. Title: 1275 Bindings for PCI Express Interconnect 0 Purpose This document specifies the modification needed in PCI bus binding to IEEE 1275, to include features provided by the next generation I/O bus, PCI Express. This provides requirements and practices for PCI Express entities like endpoints,switches,root complex,bridges and reverse bridges. 0.1 Revision History 30 Nov 2009 - Added pci-intx-not-supported property. Deleted old revision history. Deleted original authors list. 18 Feb 2010 - Modified section 3 to describe numerical representation of ARI enabled devices. Also added section 11 to describe "ari-enabled" property and added couple of more references to section 12. 1. Overview PCI Express is a high performance, general purpose I/O interconnect. It employs point-to-point interconnect and switch-based technology to deliver high level of performance and scalability.It maintains downward software compatibility with PCI Local bus specification 2.3 in a sense that software written for PCI specification 2.3 would work unchanged on a PCI Express based system. Additionally it provides advanced features like Quality of Service (QoS),Hot-plug/Hot-swap support, enhanced Power Management, advanced Error handling and Data integrity. Because of the software downward compatibility,PCI Express interconnect and devices will reuse much of the framework defined in PCI Bus Binding 2.1 with few additions and modifications where ever necessary. 2. Addition to Reference section 1.1 in PCI binding 2.1 [5] PCI Express Base Specification Revision 1.0a April 15,2003,published by PCI Special Interest Group. 3. Numerical Representation The numerical representation in PCI binding 2.1 section 2.2.1.1 has been modified slightly to accommodate extended PCI express configura- tion space of 4K bytes. Bit# 33222222 22221111 11111100 00000000 10987654 32109876 54321098 76543210 phys.hi cell: nptx00ss bbbbbbbb dddddfff rrrrrrrr phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh phys.lo cell: llllllll llllllll llllllll llllllll where: n is 0 if the address is relocatable, 1 otherwise p is 1 if the addressable region is "prefetchable", 0 otherwise t is 1 if the address is aliased (for non-relocatable I/O), below 1 MB (for Memory), or below 64 KB (for relocatable I/O). x is there to take care of extended config space address bits for PCI-E bus. x must be 0, for ss != 0 ss is the space code, denoting the address space bbbbbbbb is the 8-bit Bus Number ddddd is the 5-bit Device Number (these 5 bits may be used as extended function bits, see note related to ARI below) fff is the 3-bit Function Number rrrrrrrr is the 8-bit Register Number hh...hh is a 32-bit unsigned number ll...ll is a 32-bit unsigned number When the hh...hh and ll...ll fields are concatenated to form a larger number, hh...hh is the most significant portion and ll...ll is the least significant portion. The 'p' bit reflects the state of the "P" bit in the corresponding hardware Base Address register. Encoding of type code "ss" -------------------------- ss = 00 denotes Configuration Space, in which case: phys.hi : For PCI bus the phys.hi will be same as defined in PCI bus binding 2.1. For PCI Express the phys.hi is interpreted differently as shown below, RRRR0000 bbbbbbbb dddddfff rrrrrrrr Where, RRRR is the extended config space offset bits 8:11. This must be 0 for conventional configuration space. bbbbbbbb is the 8-bit Bus Number. ddddd is the 5-bit Device Number. (these 5 bits may be used as extended function bits, see note related to ARI below) fff is the 3-bit Function Number. rrrrrrrr is the Lower 8-bit ( 7:0 ) of Config Register Address. phys.mid : hh...hh must be zero. phys.lo : ll...ll must be zero. ss = 01 denotes I/O Space, in which case: phys.hi : p must be 0. t is set if 10-bit aliasing is present(for non-relocatable) or below 64 KB required (for relocatable). x must be 0. bbbbbbbb,ddddd,fff,rrrrrrrr identifies the region's Base Address Register. rrrrrrrr can be 0x10, 0x14, 0x18, 0x1c, 0x20 or 0x24 (for relocatable). rrrrrrrr is 0x00 for non-relocatable. phys.mid : hh...hh must be zero. phys.lo : ll...ll denotes the I/O Space address. If n is 0: ll...ll is the 32-bit offset from the start of the relocatable region of I/O Space. If n is 1: ll...ll is the 32-bit I/O Space address. ss = 10 denotes 32-bit-address Memory Space, in which case: phys.hi : p may be either 0 or 1. t is set if an address below 1 MB is required. x must be 0. bbbbbbbb,ddddd,fff,rrrrrrrr identifies the relocatable region's Base Address Register. rrrrrrrr can be 0x10, 0x14, 0x18, 0x1c, 0x20, 0x24, or 0x30 (relocatable). rrrrrrrr is 0x00 for non-relocatable. Note : 5 bits of device number may be used as extended function bits, see note related to ARI below phys.mid : hh...hh must be zero. phys.lo : ll...ll denotes the Memory Space address. If n is 0: ll...ll is the 32-bit offset from the start of the relocatable region of 32-bit address Memory Space. If n is 1: ll...ll is the 32-bit Memory Space address. NOTE : PCI Express Message space is part of PCI-E memory space. 11 denotes 64-bit-address Memory Space, in which case: phys.hi : p may be either 0 or 1. t must be 0. x must be 0. bbbbbbbb,ddddd,fff,rrrrrrrr identifies the first register of the relocatable region's Base Address Register pair. rrrrrrrr can be 0x10, 0x14, 0x18, 0x1c, or 0x20. Note : 5 bits of device number may be used as extended function bits, see note related to ARI below phys.mid : hh...hh denotes the most significant 63:32 bit of address. phys.lo : ll...ll denotes the least significant 31:00 bit of address. If n is 0: hh...hh,ll...ll is the 64-bit offset from the start of the relocatable region of 64-bit address Memory Space to the start of the subregion. If n is 1: hh...hh,ll...ll is the 64-bit Memory Space address Note related to Alternate Routing ID (ARI) support : If device supports Alternate Routing ID (ARI) forwarding extended capability and if the root-port or down-stream port above it also supports ARI capability then all of the "d" bits in the Routing ID (RID) are extended function number bits. If ARI is enabled, we are using the alternate interpretation of the RID, which used the dddd.d bits as extended function number bits. In this case the device number is implied to be always zero and the function number is extended to 8 bits (5 bits of d bits and 3 bits of f bits). The "ari-enabled" property defined in section 11 below must also be present in the bridge node directly above the ARI capable function. 4. "name","compatible" and "device_type" property For PCI Express the above properties are defined as shown below, "name" Based on the PCI Class Code register, pick a name from Table 1 as depicted in section 2.5 of PCI bus binding 2.1. If none apply, construct a name of the form pciexVVVV,DDDD, where VVVV,DDDD shall be the value of the Vendor ID and Device ID fields. VVVV and DDDD are ASCII hexadecimal numbers, lower case, without leading zeros. "compatible" The current definition of "compatible" property in section 2.5 of PCI binding 2.1 shall be modified to change the prefix from "pci" to "pciex". Hence it shall be as below, pciexVVVV,DDDD.SSSS.ssss.RR (1) pciexVVVV,DDDD.SSSS.ssss (2) pciexVVVV,DDDD.RR (4) pciexVVVV,DDDD (5) pciexclass,CCSSPP (6) pciexclass,CCSS (7) Note that entry (3) from the original list has been removed, since some vendors do allocate similar subsystem ID/subsystem vendor ID to different adapters with different vendor ID/device ID. "device_type" The "device_type" property as defined in section 3.1.1 of PCI binding 2.1 is changed from "pci" to "pciex" for PCI Express. 5. "physical-slot#" property In the section 3.1.2 for Bus-specific properties,add "physical-slot#" property for PCI Express switch downstream port or root port if a slot is implemented on the port, "physical-slot#" prop-encoded-array : integer value Read in "physical slot number"( bit:31-19) from slot capabilities register ( offset 14h in PCI express capability structure ). This h/w initialized field indicates the physical slot number attached to this port. 6. Non PCI Express specific properties to be removed Some of the PCI properties listed in PCI binding section 2.5 do not apply in case of PCI express device. Hence they should not be created for PCI Express device node. They are listed below, "min-grant" "max-latency" "fast-back-to-back" "66mhz-capable" "udf-supported" "devsel-timing" "cache-line-size" "latency-timer" 7. Upper Config Address bits Masking NOTE : PCI/PCI-X config space is limited to 256 bytes as against 4k bytes for PCI Express devices. Hence PCI Express to PCI/PCI-x bridge nexus code should zero out upper RRRR bits for config access request on the way up to filter out invalid config access in the PCI/PCI-X domain. 9. Root-port Node Some RootCompex may support Root-port(s) which is implemented via p2p bridge(s). The device tree representation of the root-port node is similar to what is described in [1] for a pci-to-pci bridge. The configuration bus number registers of root-port(s) may be implemented as 'read only' (or hardwired), and root-port behaves really like a transparent p2p bridge with pci class = 060400. Hence, the value of the compatible property for root-port node is "pciexclass,060400". 10. pci-intx-not-supported property "pci-intx-not-supported /prop-name/ , Denotes a PCI bus which does not support INTx. /boolean property/ . The presence of this property indicates that this PCIe bus does not support INTx interrupts. MSI or MSI-X should be used instead. If this property exists, it shall be published in the top level node representing the root complex. 11. "ari-enabled" property in pci-pci bridge nodes. "ari-enabled" S Standard property name to indicate that ARI is enabled in a root or downstream switch port. prop-encoded-array: No value. The existence of the property indicates that ARI is enabled in this node. 12. References [1] PCI Binding to IEEE P1275: http://noho.eng/1275/home.html#OFDbussupps [2] Proposal #430: http://noho.eng.sun.com/1275/proposals/index.html#430 [3] PCI Express Base Spec, v2.1, available at pcisig.com Note: See Section 6.13, ARI. [4] Single Root IO Virtualization, available at pcisig.com [5] PCI Binding to Open Firmware, available at http://playground.sun.com/1275