PSARC 2004/253 Advanced DDI Interrupt Framework
Submitter:  Govinda Tatti

Issues for inception (10/27/2004):

jdc-1	Syntax error: 20q3 says Update, but 20q1 says minor release
	binding.  Which is it?

jdc-2	20q9: are changes to intrstat or the probes it uses needed?

jdc-3	20q14: bus_*_intrspec and bus_intr_ctl are Consolidation
	Private, aren't they?  Why Obsolete when you could just
	remove?  Are others using these despite the lack of stability
	and documentation?

jdc-4	Are the resource management functions needed for DR on SPARC?

jdc-5	What's the distinction between DDI_FAILURE and DDI_EINVAL?

jdc-6	How does one get the mask status?  Or is that the caller's
	problem?  If I'm about to do ddi_intr_set_mask in some
	function, I may want to check if it's currently masked, so I
	know to avoid ddi_intr_clr_mask on the way out.

jdc-7	How does the new arg2 value work with
	ddi_intr_trigger_softintr?  If I call that function multiple
	times with the same ddi_softint_handle_t, but different arg2
	values, are those events queued up somewhere and delivered as
	separate invocations of the handler, or are previous
	undelivered values of arg2 forgotten?  (The old model with
	ddi_trigger_softintr was clear -- as it carried no
	information.)

jdc-8	Nits: Can I do ddi_intr_dup_handler on something allocated by
	ddi_add_intr?  I'm guessing "no," as ddi_intr_handle_t is not
	ddi_iblock_cookie_t.

jdc-9	Nits: Is DDI_INTR_TYPE_* meant to be enumerated?  (What
	happened to 3?)  Are all the new ddi_* functions Stable?

jdc-10	Nits: I assume that ddi_intr_unregister_callback can block if
	the callback is active.  Similar for ddi_intr_remove_handler
	and ddi_intr_remove_softint.

jdc-11	Nits: Does ddi_intr_alloc return DDI_SUCCESS in the behavior
	== 0 && *actualp == 0 case?  It doesn't give a return value.

jdc-12	Nits: ddi_inter_get_pri says that the value is "typically" in
	the defined range.  What does it mean if it's not?

sz-1	Nit: 20q #1: should be a "micro" change to qualify for
	update release.

sz-2	20q #15: what version information are you talking about?

sz-3	Which interfaces belong to phase 1 vs. phase 2? What's the
	consequence if phase 2 is not delivered?

sz-4	ddi_inter_get_navail(): any issues with concurrent device
	attach?

sz-5	Nit: ddi_inter_cb_t(): why two args? Same with
	ddi_intr_handler_t().

sz-6	Nit: ddi_intr_free(): block free as well?

sz-7	ddi_intr_alloc(): what's the return code if no interrupt
	is allocated and actualp is filled in?

sz-8	Q: when should driver "mask" an interrupt vs. disable?

sz-9	New softint routines: what's the value add? Are you making
	the old ones obsolete?