From bart.smaalders@sun.com Thu Jun 14 15:55:15 2007
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Date: Thu, 14 Jun 2007 15:51:46 -0700
From: Bart Smaalders <bart.smaalders@sun.com>
Subject: PSARC/2007/349  Intel Microcode Update Support
To: PSARC-EXT@sun.com
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<resend due to cut n' paste error in case number>

I'm sponsoring the attached fast track for Sherry Moore.  The requested 
release boundary is patch/micro, and the case times out on 6/20/2007.

- Bart

-- 
Bart Smaalders			Solaris Kernel Performance
barts@cyber.eng.sun.com		http://blogs.sun.com/barts

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Copyright 2007 Sun Microsystems

1. Introduction
   1.1. Project/Component Working Name:

	Intel Microcode Update Support

   1.2. Name of Document Author/Supplier:

	Sherry.Moore@sun.com

   1.3. Date of This Document:

	05/31/2007

   1.4. Name of Major Document Customer(s)/Consumer(s):
	
	PSARC

   1.5. Email Aliases:
    	1.5.1. Responsible Manager: Darrin.Johnson@sun.com
    	1.5.2. Responsible Engineer: Sherry.Moore@sun.com
    	1.5.3. Marketing Manager: Videhi.Mallela@Sun.COM
	1.5.4. Interest List: intel-ext@sun.com

2. Project Summary
   2.1. Project Description:

	The Intel P4, Xeon, P6 family and future processors have the
	capability to correct errata by loading an Intel-supplied data
	block called microcode into the processor.  This update is
	typically done by the BIOS.  To alleviate the dependencies on
	BIOS updates and to reduce system down time, it is highly
	desirable to have the microcode update ability available in the
	OS.

   2.2. Risks and Assumptions:

	The current families of processors supporting microcode update
	reject malformed microcode or microcode not intended for their
	platforms.  We assume that will not change with future
	processors.

3. Business Summary
   3.1. Problem Area:

	Currently, if a processor erratum is identified, customers have
	to either wait for a BIOS update, or for an OS patch that works
	around the erratum.  The first solution renders us at the BIOS
	vendors' mercy; the second requires releasing point patches.
	Both incurs huge delay and financial expenses.

   3.2. Market/Requester:

	Sun is currently producing Intel-based blade systems.  More
	Intel-based platforms are on the Systems Group's roadmap.  Such
	capability will no doubt benefit our customers.

   3.3. Business Justification:

	The ability to work around processor errata in the OS by
	applying microcode updates will improve RAS on our systems.

   3.4. Competitive Analysis:

	Linux has a driver for updating microcode once the system is up
	and running.  We will provide not only the ability to work
	around errata once the system is completely up and running, but
	also the ability to perform microcode update at boot time.
	Both Intel and AMD stated that microcode updates and errata
	workarounds should be performed as early as possible during
	boot.

   3.6. How will you know when you are done?:

	When we have all the software components to enable microcode
	update at boot time and at run time.


4. Technical Description:

    4.1. Technical Details

	Microcode update can be performed at early boot time by the
	operating system as each processor is being brought online.
	During early boot process the kernel would locate the
	corresponding microcode file if exists and perform the
	microcode update if necessary.  For the boot CPU the update is
	performed in mlsetup(); for the other CPUs the update is done
	in mp_startup().

	Additionally we also provide a mechanism to dynamically update
	the microcode when the system is already booted and running.
	The live update will be done via a user command through ioctl
	to a driver.  The run time update provides a way to load
	critical microcode updates to ensure system integrity without
	requiring a reboot or BIOS upgrade.

    4.2. Bug/RFE Number(s):

	6558456 Need to support microcode update on Intel platforms
    
    4.3. In Scope:

    4.4. Out of Scope:
    
    4.5. Interfaces:

    4.5.1 Command ucodeadm(1M): committed

	A new command ucodeadm(1M) is introduced to report processor
	microcode revision, install microcode files on a target system,
	and update microcode on a live system.

	# ucodeadm -h
	usage:
            ucodeadm -v
                     Shows running microcode version.

            ucodeadm -u microcode-text-file
                     Updates microcode to the latest matching version found in
                     microcode-text-file.

            ucodeadm -i [-R path] microcode-text-file
                     Installs microcode on the file system to be used
		     during subsequent boot.

	ucodeadm will be installed in /usr/sbin/.  Text for ucodeadm
	man page is attached as ucodeadm.man.txt.

	The -v option can be performed by a non-privileged user.

	The -i option requires privilege to write to the destination.

	The -u option requires privilege secpolicy_ucode_update(),
	which is currently PRIV_ALL.  The privilege checking will be
	performed by the driver.  User with "Maintenance and Repair"
	profile will be allowed to execute "/usr/sbin/ucodeadm -u" to
	update microcode.

    4.5.2 Driver ucode_drv: Uncommitted

	The ucode_drv driver will provide two ioctl commands:

	    UCODE_GET_VERSION: report microcode version
	    UCODE_UPDATE: update microcode

	The driver will be installed as /devices/pseudo/ucode.


    4.6. Doc Impact:
	
	A man page for ucodeadm(1M) will be delivered.

    4.7. Admin/Config Impact:

	New command ucodeadm(1M).

    4.8. HA Impact:

	None.

    4.10. Packaging & Delivery:

	SUNWckr, SUNWcsu, SUNWcar.i and SUNWhea will be updated.

    4.11. Security Impact:

	None.

    4.12. Dependencies:

	This project has dependency on the Intel microcode format as
	described in Intel 64 and IA-32 Architectures Software
	Developer's Manual Section 9-11 "Microcode Update Facilities".

5. Reference Documents:

	Intel 64 and IA-32 Architectures Software Developer's Manual
	Section 9-11 "Microcode Update Facilities".

	http://jurassic-x4600/~sherrym/projects/microcode/microcode.txt
	http://jurassic-x4600/~sherrym/projects/microcode/ucodeadm.man.txt

6. Resources and Schedule:
   6.1. Projected Availability:

	Q1FY08

   6.2. Cost of Effort:

	1 person for 3 months

   6.3. Cost of Capital Resources:

	No additional capital resources expected.

   6.4. Product Approval Committee requested information:
   	6.4.1. Consolidation or Component Name:

		Solaris

	6.4.3. Type of CPT Review and Approval expected:

		FastTrack

        6.4.4. Project Boundary Conditions:


	6.4.5. Is this a necessary project for OEM agreements:

		Yes.

	6.4.6. Notes:

		None.

	6.4.7. Target RTI Date/Release:
		
		5/30/2007 onnv

		6/14/2007 S10U5

	6.4.8. Target Code Design Review Date:

		6/07/2007

	6.4.9. Update approval addition:

		None.

   6.5. ARC review type:

	FastTrack

7. Prototype Availability:
   7.1. Prototype Availability:

	Prototype is available.

   7.2. Prototype Cost:

	1 person 2 months.


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From sommerfeld@sun.com Thu Jun 14 17:25:06 2007
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Date: Thu, 14 Jun 2007 20:23:23 -0400
From: Bill Sommerfeld <sommerfeld@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <4671C682.5050402@Sun.COM>
To: Bart Smaalders <bart.smaalders@sun.com>
Cc: PSARC-EXT@sun.com, Sherry Moore <Sherry.Moore@sun.com>
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On Thu, 2007-06-14 at 15:51 -0700, Bart Smaalders wrote:
> 	Both Intel and AMD stated that microcode updates and errata
> 	workarounds should be performed as early as possible during
> 	boot.

Do we know for sure whether AMD processors support a similar facility
using the same interface?  

> 5. Reference Documents:
> 
> 	Intel 64 and IA-32 Architectures Software Developer's Manual
> 	Section 9-11 "Microcode Update Facilities".
> 
> 	http://jurassic-x4600/~sherrym/projects/microcode/microcode.txt
> 	http://jurassic-x4600/~sherrym/projects/microcode/ucodeadm.man.txt

it's best to copy files like this into the case directory, both so
they're archived for posterity and also (for open cases) they become
visible to external reviewers.

I'd do it but I want to hear the author's ok first..

						- Bill




From sherry.moore@sun.com Thu Jun 14 17:50:20 2007
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Date: Thu, 14 Jun 2007 17:48:40 -0700
From: Sherry Moore <sherry.moore@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <1181867003.11308.107.camel@thunk>
To: Bill Sommerfeld <sommerfeld@sun.com>
Cc: Bart Smaalders <bart.smaalders@sun.com>, PSARC-EXT@sun.com,
        Sherry Moore <sherry.moore@sun.com>
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> Do we know for sure whether AMD processors support a similar facility
> using the same interface?  

AMD processors currently do not support microcode update by the OS.  I
am actively pushing AMD for this capability on future AMD processors.
Hopefully I could influence the interface design.  However I do
anticipate additional work when the feature does become available.

> 
> > 5. Reference Documents:
> > 
> > 	Intel 64 and IA-32 Architectures Software Developer's Manual
> > 	Section 9-11 "Microcode Update Facilities".
> > 
> > 	http://jurassic-x4600/~sherrym/projects/microcode/microcode.txt
> > 	http://jurassic-x4600/~sherrym/projects/microcode/ucodeadm.man.txt
> 
> it's best to copy files like this into the case directory, both so
> they're archived for posterity and also (for open cases) they become
> visible to external reviewers.
> 
> I'd do it but I want to hear the author's ok first..

Please copy the files for me.  Thank you.

Sherry

From sommerfeld@sun.com Thu Jun 14 18:46:30 2007
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Date: Thu, 14 Jun 2007 21:44:46 -0400
From: Bill Sommerfeld <sommerfeld@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <20070615004840.GP9695@sun.com>
To: Sherry Moore <sherry.moore@sun.com>
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On Thu, 2007-06-14 at 17:48 -0700, Sherry Moore wrote:
> > Do we know for sure whether AMD processors support a similar facility
> > using the same interface?  
> 
> AMD processors currently do not support microcode update by the OS.  I
> am actively pushing AMD for this capability on future AMD processors.
> Hopefully I could influence the interface design.  However I do
> anticipate additional work when the feature does become available.

The name chosen for the command implies that you're setting precedent
that we will enhance the current command for other processors rather
than introduce a new command for different CPU families.

I think this is a good thing -- if a different CPU needs additional
parameters beyond a file containing the microcode "blob" are needed we
can extend the CLI with more option flags.

One more question (verging on code review...):  Is this needed so early
in boot that your new /platform/i86pc/ucode directory needs to be added
to the boot archive?  

					- Bill



From bart.smaalders@sun.com Thu Jun 14 19:00:40 2007
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Date: Thu, 14 Jun 2007 18:57:08 -0700
From: Bart Smaalders <bart.smaalders@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <1181871886.11308.136.camel@thunk>
To: Bill Sommerfeld <sommerfeld@sun.com>
Cc: Sherry Moore <sherry.moore@sun.com>, PSARC-EXT@sun.com
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Bill Sommerfeld wrote:
> On Thu, 2007-06-14 at 17:48 -0700, Sherry Moore wrote:
>>> Do we know for sure whether AMD processors support a similar facility
>>> using the same interface?  
>> AMD processors currently do not support microcode update by the OS.  I
>> am actively pushing AMD for this capability on future AMD processors.
>> Hopefully I could influence the interface design.  However I do
>> anticipate additional work when the feature does become available.
> 
> The name chosen for the command implies that you're setting precedent
> that we will enhance the current command for other processors rather
> than introduce a new command for different CPU families.
> 
> I think this is a good thing -- if a different CPU needs additional
> parameters beyond a file containing the microcode "blob" are needed we
> can extend the CLI with more option flags.
> 
> One more question (verging on code review...):  Is this needed so early
> in boot that your new /platform/i86pc/ucode directory needs to be added
> to the boot archive?  

 From the one pager:

    3.4. Competitive Analysis:

	Linux has a driver for updating microcode once the system is up
	and running.  We will provide not only the ability to work
	around errata once the system is completely up and running, but
	also the ability to perform microcode update at boot time.
	Both Intel and AMD stated that microcode updates and errata
	workarounds should be performed as early as possible during
	boot.

By placing the microcode into the boot archive, it is possible to update
the microcode before the processor becomes actively used in mp_startup.
Doing the update early doesn't matter in most cases, but there like 
likely be situations where Solaris can update the microcode where other
operating systems needs a BIOS patch.


- Bart




-- 
Bart Smaalders			Solaris Kernel Performance
barts@cyber.eng.sun.com		http://blogs.sun.com/barts

From carlsonj@phorcys.east.sun.com Fri Jun 15 04:08:14 2007
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From: James Carlson <james.d.carlson@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
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Bart Smaalders writes:
> I'm sponsoring the attached fast track for Sherry Moore.  The requested 
> release boundary is patch/micro, and the case times out on 6/20/2007.

A few minor questions:

>     4.5.2 Driver ucode_drv: Uncommitted

Why not Project Private?  I'm curious about who else might want or
need to use the driver itself.

> 	    UCODE_GET_VERSION: report microcode version
> 	    UCODE_UPDATE: update microcode

For the version, is that just an ASCII text string?  I'll assume that
it is, that it's controlled by the vendor, and that we provide some
"goodly" amount of room in the ioctl interface.  (This is much less
important for the ioctl if the driver is made private.)

> 	The driver will be installed as /devices/pseudo/ucode.

Without a /dev link?  The layout of /devices is a devfs(7FS)
implementation artifact.

-- 
James Carlson, Solaris Networking              <james.d.carlson@sun.com>
Sun Microsystems / 1 Network Drive         71.232W   Vox +1 781 442 2084
MS UBUR02-212 / Burlington MA 01803-2757   42.496N   Fax +1 781 442 1677

From sherry.moore@sun.com Fri Jun 15 09:30:48 2007
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Date: Fri, 15 Jun 2007 09:29:09 -0700
From: Sherry Moore <sherry.moore@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <18034.29371.376422.227521@gargle.gargle.HOWL>
To: James Carlson <james.d.carlson@sun.com>
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> >     4.5.2 Driver ucode_drv: Uncommitted
> 
> Why not Project Private?  I'm curious about who else might want or
> need to use the driver itself.

I don't anticipate anyone else to use the driver.  I agree that
"Project Private" is more appropriate.  I chose "Uncommitted" as it's
not very clear to me what "customer-visible" entails.

> > 	    UCODE_GET_VERSION: report microcode version
> > 	    UCODE_UPDATE: update microcode
> 
> For the version, is that just an ASCII text string?  I'll assume that
> it is, that it's controlled by the vendor, and that we provide some
> "goodly" amount of room in the ioctl interface.  (This is much less
> important for the ioctl if the driver is made private.)

The version is a hex number controlled by the vendor.

> > 	The driver will be installed as /devices/pseudo/ucode.
> 
> Without a /dev link?  The layout of /devices is a devfs(7FS)
> implementation artifact.

There will be a link from /dev to /devices.  It will look like this:

# ls -l /dev/ucode 
lrwxrwxrwx   1 root     root          31 May 16 17:54 /dev/ucode -> ../devices/pseudo/ucode@0:ucode

Thanks,
Sherry

From carlsonj@phorcys.east.sun.com Fri Jun 15 09:43:16 2007
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Date: Fri, 15 Jun 2007 12:41:41 -0400
From: James Carlson <James.D.Carlson@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <20070615162909.GR9695@sun.com>
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Sherry Moore writes:
> > >     4.5.2 Driver ucode_drv: Uncommitted
> > 
> > Why not Project Private?  I'm curious about who else might want or
> > need to use the driver itself.
> 
> I don't anticipate anyone else to use the driver.  I agree that
> "Project Private" is more appropriate.  I chose "Uncommitted" as it's
> not very clear to me what "customer-visible" entails.

For Uncommitted, we might have a man page with stability warnings on
it, or we might have a white paper or some other less-formal
documentation.  "Uncommitted" is one of the so-called "Public"
stability levels, which means that we intentionally ship at least some
form of documentation for it, and we expect some users (at their own
risk) will use it.

The fact that the node exists and is visible in the file system is an
implementation detail.  (Similarly, undocumented daemons and header
files are not public interfaces.  The fact that you can "see" them
doesn't make them things you can safely use.)

> > > 	    UCODE_GET_VERSION: report microcode version
> > > 	    UCODE_UPDATE: update microcode
> > 
> > For the version, is that just an ASCII text string?  I'll assume that
> > it is, that it's controlled by the vendor, and that we provide some
> > "goodly" amount of room in the ioctl interface.  (This is much less
> > important for the ioctl if the driver is made private.)
> 
> The version is a hex number controlled by the vendor.

Hex?  OK.  (I'm sort of curious how that's reported, but if this is
now Project Private, it doesn't really matter.)

> > Without a /dev link?  The layout of /devices is a devfs(7FS)
> > implementation artifact.
> 
> There will be a link from /dev to /devices.  It will look like this:
> 
> # ls -l /dev/ucode 
> lrwxrwxrwx   1 root     root          31 May 16 17:54 /dev/ucode -> ../devices/pseudo/ucode@0:ucode

OK; thanks.

-- 
James Carlson, Solaris Networking              <james.d.carlson@sun.com>
Sun Microsystems / 1 Network Drive         71.232W   Vox +1 781 442 2084
MS UBUR02-212 / Burlington MA 01803-2757   42.496N   Fax +1 781 442 1677

From Darren.Reed@sun.com Fri Jun 15 21:31:40 2007
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Date: Fri, 15 Jun 2007 21:29:54 -0700
From: Darren.Reed@sun.com
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <4671C682.5050402@Sun.COM>
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To: Sherry.Moore@sun.com
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...

>    4.12. Dependencies:
>
>	This project has dependency on the Intel microcode format as
>	described in Intel 64 and IA-32 Architectures Software
>	Developer's Manual Section 9-11 "Microcode Update Facilities".
>  
>

Are you aware of anything in this dependency that might
prohibit the deliverables of this project being able to
function with both new and old formats of microcode
at some point in the future?

Darren


From sherry.moore@sun.com Sat Jun 16 11:14:40 2007
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Date: Sat, 16 Jun 2007 11:13:01 -0700
From: Sherry Moore <sherry.moore@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <46736742.7050200@Sun.COM>
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Cc: sherry.moore@sun.com, PSARC-EXT@sun.com
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> >   4.12. Dependencies:
> >
> >	This project has dependency on the Intel microcode format as
> >	described in Intel 64 and IA-32 Architectures Software
> >	Developer's Manual Section 9-11 "Microcode Update Facilities".
> > 
> Are you aware of anything in this dependency that might
> prohibit the deliverables of this project being able to
> function with both new and old formats of microcode
> at some point in the future?

There are explicit checks for the format version in the code, as a
result the deliverables of this project will not work with new formats
of the microcode.  The format processing portion of the project will
need to be extended should the new format become a reality.  At this
point Intel has no plans to release microcode in a different format.

Thanks,
Sherry

From Michael.Hunter@sun.com Mon Jun 18 03:04:49 2007
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Subject: Re: PSARC/2007/349  Intel Microcode Update Support
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On Thu, 14 Jun 2007 15:51:46 -0700
Bart Smaalders <bart.smaalders@sun.com> wrote:

> <resend due to cut n' paste error in case number>
> 
> I'm sponsoring the attached fast track for Sherry Moore.  The requested 
> release boundary is patch/micro, and the case times out on 6/20/2007.

It seems like the extra layer of authenticity that 2007/355 provides by
providing the updates via signed modules might to of value to our
customers.  Eventhough I believe in the almost 10 years that intel
processor updates have been available there havn't been any trojan
horses just obfusacation of mechanism, the use of what has to be known
encryption keys by this point, and embedded checksums can't be much of
a barrier to create such.  Additionally allowing these to be loaded
early in boot could make a simple denial of service trojan horse (one
that just loaded a bogus update intended to brick the machine) that
much more powerful and harder to diagnose.

		mph

From bart.smaalders@sun.com Mon Jun 18 09:44:18 2007
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Date: Mon, 18 Jun 2007 09:40:34 -0700
From: Bart Smaalders <bart.smaalders@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <20070618030309.00000827@localhost>
To: Michael Hunter <Michael.Hunter@sun.com>
Cc: PSARC-EXT@sun.com
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Michael Hunter wrote:
> On Thu, 14 Jun 2007 15:51:46 -0700
> Bart Smaalders <bart.smaalders@sun.com> wrote:
> 
>> <resend due to cut n' paste error in case number>
>>
>> I'm sponsoring the attached fast track for Sherry Moore.  The requested 
>> release boundary is patch/micro, and the case times out on 6/20/2007.
> 
> It seems like the extra layer of authenticity that 2007/355 provides by
> providing the updates via signed modules might to of value to our
> customers.  Eventhough I believe in the almost 10 years that intel
> processor updates have been available there havn't been any trojan
> horses just obfusacation of mechanism, the use of what has to be known
> encryption keys by this point, and embedded checksums can't be much of
> a barrier to create such.  Additionally allowing these to be loaded
> early in boot could make a simple denial of service trojan horse (one
> that just loaded a bogus update intended to brick the machine) that
> much more powerful and harder to diagnose.
> 
> 		mph

On the other hand, encapsulating Intel firmware inside Sun signed
modules has the following real disadvantages:

1) customers must get patch from Sun to upgrade firmware; they cannot
    install firmware released by Intel.
2) Sun needs to release 2 versions of module - 32 and 64 bit,
    currently doubling impact on boot archive size.

Sun signs their packages and patches; if the customer just gets
his updates through our normal patch stream he will get the same
protection as you're suggesting.

If the customer wishes or needs to get the latest immediately from
Intel (typical during development or bringup), he can do so easily,
using the same protection mechanisms Intel has found sufficient so far.

Unless we have some actual data indicating that additional levels of
encryption/valiudation for the microcode is needed, I'm inclined to
leave this as originally designed.

- Bart


-- 
Bart Smaalders			Solaris Kernel Performance
barts@cyber.eng.sun.com		http://blogs.sun.com/barts

From sherry.moore@sun.com Mon Jun 18 09:45:10 2007
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Date: Mon, 18 Jun 2007 09:43:32 -0700
From: Sherry Moore <sherry.moore@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <20070618030309.00000827@localhost>
To: Michael Hunter <Michael.Hunter@sun.com>
Cc: Bart Smaalders <bart.smaalders@sun.com>, PSARC-EXT@sun.com
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> It seems like the extra layer of authenticity that 2007/355 provides by
> providing the updates via signed modules might to of value to our
> customers.  Eventhough I believe in the almost 10 years that intel
> processor updates have been available there havn't been any trojan
> horses just obfusacation of mechanism, the use of what has to be known
> encryption keys by this point, and embedded checksums can't be much of
> a barrier to create such.  Additionally allowing these to be loaded
> early in boot could make a simple denial of service trojan horse (one
> that just loaded a bogus update intended to brick the machine) that
> much more powerful and harder to diagnose.

The possibility of malicious/bad microcode bricking a system has indeed
been one of our biggest concerns.  We have been talking with folks at
Intel and below is what they can guarantee:

============================================================================
From rajesh.shah@intel.com  Tue May 22 17:41:39 2007

- Intel processors have encryption/decryption in hardware to guarantee
  that they only execute microcode released from Intel intended for
  them.

- If you force feed good (i.e. original Intel) microcode to the wrong
  CPU (wrong family, model, stepping...), it will ignore the update. If
  you try to feed bad (malicious/hand-crafted) ucode to a CPU, it will
  ignore it. The actual encryption scheme we use internally may change
  over time, but of course the attempt is to make it as hard to crack
  as possible.
============================================================================

The microcode update applied by the OS does not persist through reboot
or power-cycle.  If in the most unfortunate event that a bad microcode
bricks the system, customer can recover by booting to failsafe mode,
removing /platform/i86pc/ucode, then reboot.

In any case, the premise of PSARC 2007/355 is that

    Most of other main-stream OSes provide interfaces to access firmware
    in raw-data format. But the shortage of the raw-data format is that 
    authentication check is not available. Therefore, we prefer to wrap
    the raw-data format firmware image in a kernel module so that we can
    sign and verify it by elfsign.

With processor microcode the data portion is actually an encrypted
segment to be decrypted only by the processor so authentication is
enforced by hardware.

Thanks,
Sherry

From glenn.skinner@sun.com Mon Jun 18 09:52:08 2007
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Date: Mon, 18 Jun 2007 09:39:54 -0700 (PDT)
From: Glenn Skinner <glenn.skinner@sun.com>
Subject: Re: 2007/349 [Intel Microcode Update Support]
To: PSARC-EXT@sun.com, bart.smaalders@sun.com
Reply-to: Glenn Skinner <glenn.skinner@sun.com>
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    Date: Thu, 14 Jun 2007 15:51:46 -0700
    From: Bart Smaalders <bart.smaalders@sun.com>
    Subject: PSARC/2007/349  Intel Microcode Update Support

Extracting from the proposal:

	A new command ucodeadm(1M) is introduced to report processor
	microcode revision, install microcode files on a target system,
	and update microcode on a live system.

	# ucodeadm -h
	usage:
            ucodeadm -v
                     Shows running microcode version.

            ucodeadm -u microcode-text-file
                     Updates microcode to the latest matching version found in
                     microcode-text-file.

            ucodeadm -i [-R path] microcode-text-file
                     Installs microcode on the file system to be used
		     during subsequent boot.

	ucodeadm will be installed in /usr/sbin/.  Text for ucodeadm
	man page is attached as ucodeadm.man.txt.

	The -v option can be performed by a non-privileged user.

	The -i option requires privilege to write to the destination.

	The -u option requires privilege secpolicy_ucode_update(),
	which is currently PRIV_ALL.  The privilege checking will be
	performed by the driver.  User with "Maintenance and Repair"
	profile will be allowed to execute "/usr/sbin/ucodeadm -u" to
	update microcode.

What privilege does the -i subcommand require?  How does it compare to
the secpolicy_ucode_update() privilege required for the -u subcommand?
Presumably, the two subcommands require identical privilege, but it's
best to be explicit.

		-- Glenn


From sherry.moore@sun.com Mon Jun 18 09:56:21 2007
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Date: Mon, 18 Jun 2007 09:54:40 -0700
From: Sherry Moore <sherry.moore@sun.com>
Subject: Re: 2007/349 [Intel Microcode Update Support]
In-reply-to: <200706181639.l5IGdsKf016260@ivrel.sfbay.sun.com>
To: Glenn Skinner <glenn.skinner@sun.com>
Cc: PSARC-EXT@sun.com, bart.smaalders@sun.com
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> 	The -i option requires privilege to write to the destination.
> 
> 	The -u option requires privilege secpolicy_ucode_update(),
> 	which is currently PRIV_ALL.  The privilege checking will be
> 	performed by the driver.  User with "Maintenance and Repair"
> 	profile will be allowed to execute "/usr/sbin/ucodeadm -u" to
> 	update microcode.
> 
> What privilege does the -i subcommand require?  How does it compare to
> the secpolicy_ucode_update() privilege required for the -u subcommand?
> Presumably, the two subcommands require identical privilege, but it's
> best to be explicit.

Actually I meant to say

    The -i option requires write permission to the destination.

It does not require secpolicy_ucode_update() privilege.

Thanks,
Sherry

From glenn.skinner@sun.com Mon Jun 18 11:01:41 2007
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Date: Mon, 18 Jun 2007 10:49:27 -0700 (PDT)
From: Glenn Skinner <glenn.skinner@sun.com>
Subject: Re: 2007/349 [Intel Microcode Update Support]
To: sherry.moore@sun.com
Cc: PSARC-EXT@sun.com, bart.smaalders@sun.com
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    Date: Mon, 18 Jun 2007 09:54:40 -0700
    From: Sherry Moore <sherry.moore@sun.com>
    Subject: Re: 2007/349 [Intel Microcode Update Support]

    > 	The -i option requires privilege to write to the destination.
    > 
    > 	The -u option requires privilege secpolicy_ucode_update(),
    > 	which is currently PRIV_ALL.  The privilege checking will be
    > 	performed by the driver.  User with "Maintenance and Repair"
    > 	profile will be allowed to execute "/usr/sbin/ucodeadm -u" to
    > 	update microcode.
    > 
    > What privilege does the -i subcommand require?  How does it
    > compare to the secpolicy_ucode_update() privilege required for
    > the -u subcommand?  Presumably, the two subcommands require
    > identical privilege, but it's best to be explicit.

    Actually I meant to say

        The -i option requires write permission to the destination.

    It does not require secpolicy_ucode_update() privilege.

Does that create a way for a user with privilege less than
secpolicy_ucode_update() to arrange to update microcode by writing it
to the location from which it will be read on a subsequent boot and
then rebooting?

		-- Glenn


From sherry.moore@sun.com Mon Jun 18 11:12:06 2007
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Date: Mon, 18 Jun 2007 11:10:26 -0700
From: Sherry Moore <sherry.moore@sun.com>
Subject: Re: 2007/349 [Intel Microcode Update Support]
In-reply-to: <200706181749.l5IHnRPB016453@ivrel.sfbay.sun.com>
To: Glenn Skinner <glenn.skinner@sun.com>
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>     Actually I meant to say
> 
>         The -i option requires write permission to the destination.
> 
>     It does not require secpolicy_ucode_update() privilege.
> 
> Does that create a way for a user with privilege less than
> secpolicy_ucode_update() to arrange to update microcode by writing it
> to the location from which it will be read on a subsequent boot and
> then rebooting?
> 
> 		-- Glenn

Yes.  If a system allows a user with privilege less than
secpolicy_ucode_update() to write to /platform/i86pc/ucode, which is of
the following mode,

    d none platform/i86pc/ucode 755 root sys

then this user will be able to arrange microcode update by writing it
to the location to be used on subsequent boot.

Thanks,
Sherry

From casper@holland.sun.com Mon Jun 18 11:16:27 2007
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From: Casper.Dik@sun.com
Subject: Re: 2007/349 [Intel Microcode Update Support]
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>>     Actually I meant to say
>> 
>>         The -i option requires write permission to the destination.
>> 
>>     It does not require secpolicy_ucode_update() privilege.
>> 
>> Does that create a way for a user with privilege less than
>> secpolicy_ucode_update() to arrange to update microcode by writing it
>> to the location from which it will be read on a subsequent boot and
>> then rebooting?
>> 
>> 		-- Glenn
>
>Yes.  If a system allows a user with privilege less than
>secpolicy_ucode_update() to write to /platform/i86pc/ucode, which is of
>the following mode,
>
>    d none platform/i86pc/ucode 755 root sys
>
>then this user will be able to arrange microcode update by writing it
>to the location to be used on subsequent boot.

But such a location would normally either require all privileges
or root; stronger protections are currently not on offer.

And since the microcode is signed, the only risk is perhaps downgrading?

Casper

From sommerfeld@sun.com Mon Jun 18 11:40:37 2007
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Date: Mon, 18 Jun 2007 14:38:55 -0400
From: Bill Sommerfeld <sommerfeld@sun.com>
Subject: Re: 2007/349 [Intel Microcode Update Support]
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On Mon, 2007-06-18 at 20:14 +0200, Casper.Dik@sun.com wrote:
> And since the microcode is signed, the only risk is perhaps downgrading?

If the reason for the firmware upgrade is to fix a security hole,
preventing downgrades is important.

Though there's an additional risk -- that the undocumented signature
validation mechanism for the firmware upgrade blob is reverse engineered
and found to be weak.  I find it worth noting that the structures
defined in this case include 32-bit checksums.  I really hope that's not
the only "signature" involved...

						- Bill




From Nicolas.Williams@sun.com Mon Jun 18 11:42:54 2007
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Date: Mon, 18 Jun 2007 13:40:13 -0500
From: Nicolas Williams <Nicolas.Williams@sun.com>
Subject: Re: 2007/349 [Intel Microcode Update Support]
In-reply-to: <1182191935.28165.15.camel@thunk>
To: Bill Sommerfeld <sommerfeld@sun.com>
Cc: Casper.Dik@sun.com, Sherry Moore <Sherry.Moore@sun.com>,
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On Mon, Jun 18, 2007 at 02:38:55PM -0400, Bill Sommerfeld wrote:
> Though there's an additional risk -- that the undocumented signature
> validation mechanism for the firmware upgrade blob is reverse engineered
> and found to be weak.  I find it worth noting that the structures
> defined in this case include 32-bit checksums.  I really hope that's not
> the only "signature" involved...

Are the algorithms used by Intel public?  If not then that's an
additional reason to do our own signing.

From sommerfeld@Sun.COM Mon Jun 18 12:27:17 2007
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From: Bill Sommerfeld <sommerfeld@Sun.COM>
Subject: Re: 2007/349 [Intel Microcode Update Support]
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On Mon, 2007-06-18 at 13:40 -0500, Nicolas Williams wrote:
> Are the algorithms used by Intel public?  If not then that's an
> additional reason to do our own signing.

They're not.  Starting from:
http://developer.intel.com/products/processor/manuals/index.htm

I found:

"Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3A: System Programming Guide"

see section 9.11 of:

http://developer.intel.com/design/processor/manuals/253668.pdf

assuming I'm reading this correctly, intel recommends that (a) software
using this interface verify that the microcode blob checksums correctly
(using a sum of the blob interpreted as an array of 32-bit integers)
before attempting the load, and (b) software verify that the the
microcode blob is for the CPU that's running.

The document also states that the CPU will do additional tests before
accepting the blob but says nothing about what they are or how strong
they are.

BTW, to make it easier to find, I put a copy of this PDF into the case
directory as "ia32-sdm-3A.pdf".

					- Bill










From Michael.Hunter@sun.com Mon Jun 18 14:30:14 2007
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Date: Mon, 18 Jun 2007 14:28:28 -0700
From: Michael Hunter <Michael.Hunter@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
In-reply-to: <20070618164332.GB12473@sun.com>
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On Mon, 18 Jun 2007 09:43:32 -0700
Sherry Moore <Sherry.Moore@Sun.COM> wrote:

[...]
> - If you force feed good (i.e. original Intel) microcode to the wrong
>   CPU (wrong family, model, stepping...), it will ignore the update. If
>   you try to feed bad (malicious/hand-crafted) ucode to a CPU, it will
>   ignore it. The actual encryption scheme we use internally may change
>   over time, but of course the attempt is to make it as hard to crack
>   as possible.
[...]

This was the part I was missing.  I knew there was encryption on the
data part but I thought that was undone before feeding to the
processor.  If its done afterwards that sounds better.  Its smacks of
security by obscurity that we have to take them at their word that it
will be "as hard to crack as possible" with no chance for a community
wide analysis but it does mediate the concern some and (fwiw) might
transfer the blame if the protection was broken and used in a malicious
manner. That together with the fact that the only time they would be
doing this with suspect ucode would be if they needed a microcode
update inbetween OS updates seems reasonable to me.

			mph

From Nicolas.Williams@sun.com Mon Jun 18 14:38:35 2007
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From: Nicolas Williams <Nicolas.Williams@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
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On Mon, Jun 18, 2007 at 02:28:28PM -0700, Michael Hunter wrote:
> This was the part I was missing.  I knew there was encryption on the
> data part but I thought that was undone before feeding to the
> processor.  If its done afterwards that sounds better.  Its smacks of
> security by obscurity that we have to take them at their word that it
> will be "as hard to crack as possible" with no chance for a community
> wide analysis but it does mediate the concern some and (fwiw) might
> transfer the blame if the protection was broken and used in a malicious
> manner. That together with the fact that the only time they would be
> doing this with suspect ucode would be if they needed a microcode
> update inbetween OS updates seems reasonable to me.

Is there security value in Intel's encrypting this data?  IMO, not much.

I suspect that's there only for protecting Intel's trade secrets, not
for security.  For Intel's customers the security value should come from
the cryptographic integrity protection scheme used by Intel, but we have
no details, therefore can't form an opinion as to how good that is.

I think providing additional security here through signing files would
be good, but I'm not sure that the ARC cares or should care to force the
matter, particularly if adding this module to the boot archive has
significantly negative impact on boot archive size.

Nico
-- 

From Sherry.Moore@Sun.COM Mon Jun 18 14:39:33 2007
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Date: Mon, 18 Jun 2007 14:37:53 -0700
From: Sherry Moore <Sherry.Moore@Sun.COM>
Subject: Re: 2007/349 [Intel Microcode Update Support]
In-reply-to: <1182194734.28165.28.camel@thunk>
To: Bill Sommerfeld <sommerfeld@Sun.COM>
Cc: Nicolas Williams <Nicolas.Williams@Sun.COM>, Casper.Dik@Sun.COM,
        Sherry Moore <Sherry.Moore@Sun.COM>,
        Glenn Skinner <glenn.skinner@Sun.COM>, PSARC-EXT@Sun.COM
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You are reading the document correctly.

The implementation of this project will
    1. verify the 32-bit unsigned checksum
    2. verify that microcode is intended for the target CPU
before attempting to apply the microcode.

The checksum algorithm is very weak and I think it is only in place to
filter out the most obvious hacks/mistakes.  The true and most vigorous
authentication is done by hardware.

Thanks,
Sherry

On Mon, Jun 18, 2007 at 03:25:34PM -0400, Bill Sommerfeld wrote:
> On Mon, 2007-06-18 at 13:40 -0500, Nicolas Williams wrote:
> > Are the algorithms used by Intel public?  If not then that's an
> > additional reason to do our own signing.
> 
> They're not.  Starting from:
> http://developer.intel.com/products/processor/manuals/index.htm
> 
> I found:
> 
> "Intel 64 and IA-32 Architectures Software Developer's Manual
> Volume 3A: System Programming Guide"
> 
> see section 9.11 of:
> 
> http://developer.intel.com/design/processor/manuals/253668.pdf
> 
> assuming I'm reading this correctly, intel recommends that (a) software
> using this interface verify that the microcode blob checksums correctly
> (using a sum of the blob interpreted as an array of 32-bit integers)
> before attempting the load, and (b) software verify that the the
> microcode blob is for the CPU that's running.
> 
> The document also states that the CPU will do additional tests before
> accepting the blob but says nothing about what they are or how strong
> they are.
> 
> BTW, to make it easier to find, I put a copy of this PDF into the case
> directory as "ia32-sdm-3A.pdf".
> 
> 					- Bill

From edward.pilatowicz@sun.com Mon Jun 18 22:41:49 2007
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Date: Mon, 18 Jun 2007 22:40:10 -0700
From: Edward Pilatowicz <edward.pilatowicz@sun.com>
Subject: Re: PSARC/2007/349  Intel Microcode Update Support
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On Mon, Jun 18, 2007 at 09:40:34AM -0700, Bart Smaalders wrote:
> Michael Hunter wrote:
> >On Thu, 14 Jun 2007 15:51:46 -0700
> >Bart Smaalders <bart.smaalders@sun.com> wrote:
> >
> >><resend due to cut n' paste error in case number>
> >>
> >>I'm sponsoring the attached fast track for Sherry Moore.  The requested
> >>release boundary is patch/micro, and the case times out on 6/20/2007.
> >
> >It seems like the extra layer of authenticity that 2007/355 provides by
> >providing the updates via signed modules might to of value to our
> >customers.  Eventhough I believe in the almost 10 years that intel
> >processor updates have been available there havn't been any trojan
> >horses just obfusacation of mechanism, the use of what has to be known
> >encryption keys by this point, and embedded checksums can't be much of
> >a barrier to create such.  Additionally allowing these to be loaded
> >early in boot could make a simple denial of service trojan horse (one
> >that just loaded a bogus update intended to brick the machine) that
> >much more powerful and harder to diagnose.
> >
> >		mph
>
> On the other hand, encapsulating Intel firmware inside Sun signed
> modules has the following real disadvantages:
>
> 1) customers must get patch from Sun to upgrade firmware; they cannot
>    install firmware released by Intel.
> 2) Sun needs to release 2 versions of module - 32 and 64 bit,
>    currently doubling impact on boot archive size.
>

it's probably worth mentioning that while we would need to release two
versions of the module, this really wouldn't double the size of data
added to a boot archive since there are seperate boot archives for
32 and 64-bit booting.

> Sun signs their packages and patches; if the customer just gets
> his updates through our normal patch stream he will get the same
> protection as you're suggesting.
>
> If the customer wishes or needs to get the latest immediately from
> Intel (typical during development or bringup), he can do so easily,
> using the same protection mechanisms Intel has found sufficient so far.
>
> Unless we have some actual data indicating that additional levels of
> encryption/valiudation for the microcode is needed, I'm inclined to
> leave this as originally designed.
>
> - Bart
>
>
> --
> Bart Smaalders			Solaris Kernel Performance
> barts@cyber.eng.sun.com		http://blogs.sun.com/barts

From bart.smaalders@sun.com Wed Jun 20 19:06:50 2007
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Date: Wed, 20 Jun 2007 19:03:08 -0700
From: Bart Smaalders <bart.smaalders@sun.com>
Subject: PSARC 2007/349  Intel Microcode Update Suppor
To: PSARC-EXT@sun.com
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This fast track was approved at today's PSARC meeting.

- Bart

-- 
Bart Smaalders			Solaris Kernel Performance
barts@cyber.eng.sun.com		http://blogs.sun.com/barts

