New Events| | ereport.cpu.intel |
| Description: | Intel ereports |
|
| [leaf] | ereport.cpu.intel.bus_interconnect |
| Description: | BUS_L{0,1,2,G}_{SRC,RES,OBS}_{RRRR}_-_{TIMEOUT,NOTIMEOUT}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.bus_interconnect_io |
| Description: | BUS_L{0,1,2,G}_{SRC,RES,OBS}_{RRRR}_IO_{TIMEOUT,NOTIMEOUT}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.bus_interconnect_io_uc |
| Description: | BUS_L{0,1,2,G}_{SRC,RES,OBS}_{RRRR}_IO_{TIMEOUT,NOTIMEOUT}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.bus_interconnect_memory |
| Description: | BUS_L{0,1,2,G}_{SRC,RES,OBS}_{RRRR}_M_{TIMEOUT,NOTIMEOUT}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.bus_interconnect_memory_uc |
| Description: | BUS_L{0,1,2,G}_{SRC,RES,OBS}_{RRRR}_M_{TIMEOUT,NOTIMEOUT}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.bus_interconnect_uc |
| Description: | BUS_L{0,1,2,G}_{SRC,RES,OBS}_{RRRR}_-_{TIMEOUT,NOTIMEOUT}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.cache |
| Description: | Generic Memory Hierarchy generic cache error; also GCACHELG_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.cache_uc |
| Description: | Generic Memory Hierarchy generic cache error; also GCACHELG_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.dcache |
| Description: | DCACHELG_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.dcache_uc |
| Description: | DCACHELG_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.dtlb |
| Description: | DTLBLG_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.dtlb_uc |
| Description: | DTLBLG_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.external |
| Description: | Simple error class - #MC from external source |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.frc |
| Description: | Simple error class - functional redundancy check |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.icache |
| Description: | ICACHELG_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.icache_uc |
| Description: | ICACHELG_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.internal_timer |
| Description: | Simple error class - internal timer error |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.internal_unclassified |
| Description: | Simple error class - internal unclassified |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.itlb |
| Description: | ITLBLG_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.itlb_uc |
| Description: | ITLBLG_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0cache |
| Description: | Generic Memory Hierarchy level 0 cache error; also GCACHEL0_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0cache_uc |
| Description: | Generic Memory Hierarchy level 0 cache error; also GCACHEL0_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0dcache |
| Description: | DCACHEL0_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0dcache_uc |
| Description: | DCACHEL0_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0dtlb |
| Description: | DTLBL0_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0dtlb_uc |
| Description: | DTLBL0_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0icache |
| Description: | ICACHEL0_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0icache_uc |
| Description: | ICACHEL0_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0itlb |
| Description: | ITLBL0_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0itlb_uc |
| Description: | ITLBL0_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0tlb |
| Description: | GTLBL0_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l0tlb_uc |
| Description: | GTLBL0_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1cache |
| Description: | Generic Memory Hierarchy level 1 cache error; also GCACHEL1_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1cache_uc |
| Description: | Generic Memory Hierarchy level 1 cache error; also GCACHEL1_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1dcache |
| Description: | DCACHEL1_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1dcache_uc |
| Description: | DCACHEL1_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1dtlb |
| Description: | DTLBL1_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1dtlb_uc |
| Description: | DTLBL1_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1icache |
| Description: | ICACHEL1_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1icache_uc |
| Description: | ICACHEL1_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1itlb |
| Description: | ITLBL1_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1itlb_uc |
| Description: | ITLBL1_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1tlb |
| Description: | GTLBL1_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l1tlb_uc |
| Description: | GTLBL1_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2cache |
| Description: | Generic Memory Hierarchy level 2 cache error; also GCACHEL2_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2cache_uc |
| Description: | Generic Memory Hierarchy level 2 cache error; also GCACHEL2_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2dcache |
| Description: | DCACHEL2_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2dcache_uc |
| Description: | DCACHEL2_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2dtlb |
| Description: | DTLBL2_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2dtlb_uc |
| Description: | DTLBL2_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2icache |
| Description: | ICACHEL2_{RRRR}_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2icache_uc |
| Description: | ICACHEL2_{RRRR}_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2itlb |
| Description: | ITLBL2_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2itlb_uc |
| Description: | ITLBL2_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2tlb |
| Description: | GTLBL2_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.l2tlb_uc |
| Description: | GTLBL2_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.microcode_rom_parity |
| Description: | Simple error class - microcode parity |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| | ereport.cpu.intel.nb |
| Description: | Intel northbridge ereports |
|
| [leaf] | ereport.cpu.intel.nb.dma |
| Description: | Northbridge dma controller error |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | PCISTS | uint16_t | PCI status | |
| PEXDEVSTS | uint16_t | PCI Express device status | |
|
| [leaf] | ereport.cpu.intel.nb.esi |
| Description: | Southbridge error |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | AERRCAPCTRL | uint32_t | PCI Express advanced error capabilities and control | |
| CORERRSTS | uint32_t | PCI Express correctable error status | |
| PEX | uint8_t | hostbridge | |
| PEXDEVSTS | uint32_t | PCI Express device status | |
| PEX_FAT_FERR | uint32_t | First fatal error register for PCI Express hostbridge | |
| PEX_FAT_NERR | uint32_t | Next fatal error register for PCI Express hostbridge | |
| PEX_NF_CORR_FERR | uint32_t | First non-fatal or correctable error register for PCI Express hostbridge | |
| PEX_NF_CORR_NERR | uint32_t | Next non-fatal or correctable error register for PCI Express hostbridge | |
| RPERRSID | uint32_t | PCI Express error source id | |
| RPERRSTS | uint32_t | PCI Express root error status | |
| UNCERRSEV | uint32_t | Uncorrectable error severity | |
| UNCERRSTS | uint32_t | PCI Express uncorrectable error status | |
| intel-error-list | string | Intel MCH data sheet error list number | |
|
| | ereport.cpu.intel.nb.fbd |
| Description: | Intel memory dimm ereports |
|
| [leaf] | ereport.cpu.intel.nb.fbd.alert |
| Description: | Fatal memory alert on dimm |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | Inherit version 0 from ereport.cpu.intel.nb.fbd | | NRECMEMA | uint16_t | Non-Recoverable Memory Error Log Register A | |
| NRECMEMB | uint32_t | Non-Recoverable Memory Error Log Register B | |
| bank | int | Bank of the failed request | |
| cas | int | Column address of the failed request | |
| dimm | int | Dimm of the failed request | |
| intel-error-list | string | Intel MCH data sheet error list number | |
| offset | uint64_t | offset in dimm of the failed request | |
| physaddr | uint64_t | Physical address of the failed request | |
| rank | int | Rank of the failed request | |
| ras | int | Row address of the failed request | |
|
| [leaf] | ereport.cpu.intel.nb.fbd.ch |
| Description: | Error on memory channel |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | Inherit version 0 from ereport.cpu.intel.nb.fbd | | RECMEMA | uint16_t | Non-Recoverable Memory Error Log Register A | |
| RECMEMB | uint32_t | Non-Recoverable Memory Error Log Register B | |
| bank | int | Bank of the failed request | |
| cas | int | Column address of the failed request | |
| dimm | int | Dimm of the failed request | |
| intel-error-list | string | Intel MCH data sheet error list number | |
| offset | uint64_t | offset in dimm of the failed request | |
| physaddr | uint64_t | Physical address of the failed request | |
| rank | int | Rank of the failed request | |
| ras | int | Row address of the failed request | |
|
| [leaf] | ereport.cpu.intel.nb.fbd.crc |
| Description: | CRC error on dimm replay |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | Inherit version 0 from ereport.cpu.intel.nb.fbd | | NRECMEMA | uint16_t | Non-Recoverable Memory Error Log Register A | |
| NRECMEMB | uint32_t | Non-Recoverable Memory Error Log Register B | |
| bank | int | Bank of the failed request | |
| cas | int | Column address of the failed request | |
| dimm | int | Dimm of the failed request | |
| intel-error-list | string | Intel MCH data sheet error list number | |
| offset | uint64_t | offset in dimm of the failed request | |
| physaddr | uint64_t | Physical address of the failed request | |
| rank | int | Rank of the failed request | |
| ras | int | Row address of the failed request | |
|
| [leaf] | ereport.cpu.intel.nb.fbd.ma |
| Description: | Memory alert on write |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | Inherit version 0 from ereport.cpu.intel.nb.fbd | | RECMEMA | uint16_t | Non-Recoverable Memory Error Log Register A | |
| RECMEMB | uint32_t | Non-Recoverable Memory Error Log Register B | |
| bank | int | Bank of the failed request | |
| cas | int | Column address of the failed request | |
| dimm | int | Dimm of the failed request | |
| intel-error-list | string | Intel MCH data sheet error list number | |
| offset | uint64_t | offset in dimm of the failed request | |
| physaddr | uint64_t | Physical address of the failed request | |
| rank | int | Rank of the failed request | |
| ras | int | Row address of the failed request | |
|
| [leaf] | ereport.cpu.intel.nb.fbd.otf |
| Description: | Over temperature on dimm channel with intelligent throttling disabled |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | Inherit version 0 from ereport.cpu.intel.nb.fbd | | NRECMEMA | uint16_t | Non-Recoverable Memory Error Log Register A | |
| NRECMEMB | uint32_t | Non-Recoverable Memory Error Log Register B | |
| bank | int | Bank of the failed request | |
| cas | int | Column address of the failed request | |
| dimm | int | Dimm of the failed request | |
| intel-error-list | string | Intel MCH data sheet error list number | |
| offset | uint64_t | offset in dimm of the failed request | |
| physaddr | uint64_t | Physical address of the failed request | |
| rank | int | Rank of the failed request | |
| ras | int | Row address of the failed request | |
|
| [leaf] | ereport.cpu.intel.nb.fbd.reset_timeout |
| Description: | Non Redundant Fast Reset Timeout |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | Inherit version 0 from ereport.cpu.intel.nb.fbd | | NRECMEMA | uint16_t | Non-Recoverable Memory Error Log Register A | |
| NRECMEMB | uint32_t | Non-Recoverable Memory Error Log Register B | |
| bank | int | Bank of the failed request | |
| cas | int | Column address of the failed request | |
| dimm | int | Dimm of the failed request | |
| intel-error-list | string | Intel MCH data sheet error list number | |
| offset | uint64_t | offset in dimm of the failed request | |
| physaddr | uint64_t | Physical address of the failed request | |
| rank | int | Rank of the failed request | |
| ras | int | Row address of the failed request | |
|
| [leaf] | ereport.cpu.intel.nb.fsb |
| Description: | Front Side Bus error |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | FERR_FAT_FSB | uint8_t | First fatal error register for Front side bus | |
| FERR_NF_FSB | uint8_t | First Non-fatal error register for Front side bus | |
| NERR_FAT_FSB | uint8_t | Next fatal error register for Front side bus | |
| NERR_NF_FSB | int | Next Non-fatal error register for Front side bus | |
| NRECFSB | uint32_t | Non recoverable front side bus error log register | |
| NRECFSB_ADDR | uint64_t | Non recoverable front side bus address error log register | |
| RECFSB | uint32_t | Recoverable front side bus error log register | |
| fsb | uint8_t | front side bus | |
| intel-error-list | string | Intel MCH data sheet error list number | |
|
| [leaf] | ereport.cpu.intel.nb.ie |
| Description: | Northbridge internal error |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | FERR_FAT_INT | uint8_t | First fatal internal error for northbridge | |
| FERR_NF_INT | uint8_t | First non-fatal internal error for northbridge | |
| NERR_FAT_INT | uint8_t | Next fatal internal error for northbridge | |
| NERR_NF_INT | uint8_t | Next non-fatal internal error for northbridge | |
| NRECINT | uint32_t | Non recoverable internal Memory Controller Hub log register | |
| NRECSF | uint64_t | Non recoverable error control information of snoop filter | |
| RECINT | uint32_t | Recoverable internal Memory Controller Hub log register | |
| RECSF | uint64_t | Recoverable error control information of snoop filter | |
| intel-error-list | string | Intel MCH data sheet error list number | |
|
| [leaf] | ereport.cpu.intel.nb.mem_ce |
| Description: | Correctable ECC error |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | RECMEMA | uint16_t | Non-Recoverable Memory Error Log Register A | |
| RECMEMB | uint32_t | Non-Recoverable Memory Error Log Register B | |
| bank | int | Bank of the failed request | |
| cas | int | Column address of the failed request | |
| dimm | int | Dimm of the failed request | |
| intel-error-list | string | Intel MCH data sheet error list number | |
| offset | uint64_t | offset in dimm of the failed request | |
| physaddr | uint64_t | Physical address of the failed request | |
| rank | int | Rank of the failed request | |
| ras | int | Row address of the failed request | |
|
| [leaf] | ereport.cpu.intel.nb.mem_ds |
| Description: | Memory spare dimm rank deployed by memory controller |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | RECMEMA | uint16_t | Non-Recoverable Memory Error Log Register A | |
| RECMEMB | uint32_t | Non-Recoverable Memory Error Log Register B | |
| bank | int | Bank of the failed request | |
| cas | int | Column address of the failed request | |
| dimm | int | Dimm of the failed request | |
| intel-error-list | string | Intel MCH data sheet error list number | |
| offset | uint64_t | offset in dimm of the failed request | |
| physaddr | uint64_t | Physical address of the failed request | |
| rank | int | Rank of the failed request | |
| ras | int | Row address of the failed request | |
|
| [leaf] | ereport.cpu.intel.nb.mem_ue |
| Description: | Uncorrectable ECC error |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | RECMEMA | uint16_t | Non-Recoverable Memory Error Log Register A | |
| RECMEMB | uint32_t | Non-Recoverable Memory Error Log Register B | |
| bank | int | Bank of the failed request | |
| cas | int | Column address of the failed request | |
| dimm | int | Dimm of the failed request | |
| intel-error-list | string | Intel MCH data sheet error list number | |
| offset | uint64_t | offset in dimm of the failed request | |
| physaddr | uint64_t | Physical address of the failed request | |
| rank | int | Rank of the failed request | |
| ras | int | Row address of the failed request | |
|
| [leaf] | ereport.cpu.intel.nb.pex |
| Description: | PCI Express error |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | | AERRCAPCTRL | uint32_t | PCI Express advanced error capabilities and control | |
| CORERRSTS | uint32_t | PCI Express correctable error status | |
| PEX | uint8_t | hostbridge | |
| PEXDEVSTS | uint32_t | PCI Express device status | |
| PEX_FAT_FERR | uint32_t | First fatal error register for PCI Express hostbridge | |
| PEX_FAT_NERR | uint32_t | Next fatal error register for PCI Express hostbridge | |
| PEX_NF_CORR_FERR | uint32_t | First non-fatal or correctable error register for PCI Express hostbridge | |
| PEX_NF_CORR_NERR | uint32_t | Next non-fatal or correctable error register for PCI Express hostbridge | |
| RPERRSID | uint32_t | PCI Express error source id | |
| RPERRSTS | uint32_t | PCI Express root error status | |
| UNCERRSEV | uint32_t | Uncorrectable error severity | |
| UNCERRSTS | uint32_t | PCI Express uncorrectable error status | |
| intel-error-list | string | Intel MCH data sheet error list number | |
|
| [leaf] | ereport.cpu.intel.nb.unknown |
| Description: | Northbridge unknown error |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | Inherit version 0 from ereport.cpu.intel.nb | |
| [leaf] | ereport.cpu.intel.tlb |
| Description: | GTLBLG_ERR |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.tlb_uc |
| Description: | GTLBLG_ERR - uncorrected |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| compound_errorname | string | MCA interpretation for this compound error | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.unclassified |
| Description: | Simple error class - unclassified |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| [leaf] | ereport.cpu.intel.unknown |
| Description: | Unknown error type |
Payload 0| Inherit version 0 from ereport | | Inherit version 0 from ereport.cpu | | Inherit version 0 from ereport.cpu.intel | | IA32_MCG_STATUS | uint64_t | MCG_STATUS value when MCA banks were read | |
| IA32_MCi_ADDR | uint64_t | MCi_ADDR raw value, included if MCi_STATUS.ADDRV indicates address valid | |
| IA32_MCi_MISC | uint64_t | MCi_MISC raw value, included if MCi_STATUS.MISCV indicates misc register valid | |
| IA32_MCi_STATUS | uint64_t | MCi_STATUS raw value | |
| bank_msr_offset | uint64_t | MSR offset of MCi_CTL register for this bank | |
| bank_number | uint8_t | MCA bank number - N'th set of MCi{CTL,STATUS,ADDR,MISC} | |
| error_code | uint16_t | MCi_STATUS architectural error code - bits 15-0 | |
| error_enabled | boolean value | Set if MCi_STATUS.EN indicates #MC was enabled for this error type | |
| error_uncorrected | boolean value | Set if MCi_STATUS.UC indicates uncorrected | |
| ip | uint64_t | Instruction pointer for machine checks, if MCG_STATUS.EIPV | |
| machine_check_in_progress | boolean value | MCG_STATUS.MCIP | |
| model_specific_error_code | uint16_t | MCi_STATUS model-specific error code - bits 31-16 | |
| overflow | boolean_value | Set if MCi_STATUS.OVER indicates an overflow | |
| privileged | boolean value | For #MC indicates if interrupted IP was kernel/user | |
| processor_context_corrupt | boolean value | Set if MCi_STATUS.PCC indicates corruption | |
| threshold_based_error_status | string | No tracking, Green - below threshold, Yellow - above threshold, Reserved | |
|
| | fault.cpu.intel |
| Description: | Intel Faults |
|
| [leaf] | fault.cpu.intel.bus_interconnect |
| Description: | Bus/Interconnect fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.bus_interconnect_io |
| Description: | IO fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.bus_interconnect_memory |
| Description: | Memory fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.cache |
| Description: | Cache Fault (which one unknown) |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.dcache |
| Description: | Data Cache Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.dtlb |
| Description: | Data TLB Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.icache |
| Description: | Instruction Cache Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.internal |
| Description: | Internal chip error diagnosed from most simple error types |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.itlb |
| Description: | Instruction TLB Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l0cache |
| Description: | Level 0 Cache Fault (which one unknown) |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l0dcache |
| Description: | Level 0 Data Cache Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l0dtlb |
| Description: | Level 0 Data TLB Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l0icache |
| Description: | Level 0 Instruction Cache Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l0itlb |
| Description: | Level 0 Instruction TLB Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l0tlb |
| Description: | Level 0 TLB Fault (which TLB unknown) |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l1cache |
| Description: | Level 1 Cache Fault (which one unknown) |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l1dcache |
| Description: | Level 1 Data Cache Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l1dtlb |
| Description: | Level 1 Data TLB Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l1icache |
| Description: | Level 1 Instruction Cache Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l1itlb |
| Description: | Level 1 Instruction TLB Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l1tlb |
| Description: | Level 1 TLB Fault (which TLB unknown) |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l2cache |
| Description: | Level 2 Cache Fault (which one unknown) |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l2dcache |
| Description: | Level 2 Data Cache Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l2dtlb |
| Description: | Level 2 Data TLB Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l2icache |
| Description: | Level 2 Instruction Cache Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l2itlb |
| Description: | Level 2 Instruction TLB Fault |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| [leaf] | fault.cpu.intel.l2tlb |
| Description: | Level 2 TLB Fault (which TLB unknown) |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| | fault.cpu.intel.nb |
| Description: | Intel northbridge Faults |
|
| [leaf] | fault.cpu.intel.nb.dma |
| Description: | northbridge dma controller error |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | | Inherit version 0 from fault.cpu.intel.nb | |
| [leaf] | fault.cpu.intel.nb.fsb |
| Description: | Front Side Bus error |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | | Inherit version 0 from fault.cpu.intel.nb | |
| [leaf] | fault.cpu.intel.nb.ie |
| Description: | northbridge internal error |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | | Inherit version 0 from fault.cpu.intel.nb | |
| [leaf] | fault.cpu.intel.tlb |
| Description: | TLB Fault (which TLB unknown) |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.cpu | | Inherit version 0 from fault.cpu.intel | |
| | fault.memory.intel |
| Description: | Intel memory Faults |
|
| [leaf] | fault.memory.intel.dimm_ce |
| Description: | The number of errors associated with this memory module has exceeded acceptable levels. |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | |
| [leaf] | fault.memory.intel.dimm_ue |
| Description: | The number of errors associated with this memory module has exceeded acceptable levels. |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | |
| | fault.memory.intel.fbd |
| Description: | Intel memory dimm Faults |
|
| [leaf] | fault.memory.intel.fbd.alert |
| Description: | memory dimm alert |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | | Inherit version 0 from fault.memory.intel.fbd | |
| [leaf] | fault.memory.intel.fbd.berr |
| Description: | memory dimm channel error |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | | Inherit version 0 from fault.memory.intel.fbd | |
| [leaf] | fault.memory.intel.fbd.ch |
| Description: | memory dimm channel error |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | | Inherit version 0 from fault.memory.intel.fbd | |
| [leaf] | fault.memory.intel.fbd.crc |
| Description: | memory dimm CRC error |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | | Inherit version 0 from fault.memory.intel.fbd | |
| [leaf] | fault.memory.intel.fbd.mem_ds |
| Description: | memory dimm spare rank deployed |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | | Inherit version 0 from fault.memory.intel.fbd | |
| [leaf] | fault.memory.intel.fbd.otf |
| Description: | memory dimm channel thermal event |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | | Inherit version 0 from fault.memory.intel.fbd | |
| [leaf] | fault.memory.intel.fbd.reset_timeout |
| Description: | memory dimm non redundant fast reset timeout |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | | Inherit version 0 from fault.memory.intel.fbd | |
| [leaf] | fault.memory.intel.page_ce |
| Description: | Memory module errors exceeding acceptable levels |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | |
| [leaf] | fault.memory.intel.page_ue |
| Description: | The number of errors associated with this memory page has exceeded acceptable levels. |
Payload 0| Inherit version 0 from fault | | Inherit version 0 from fault.memory | | Inherit version 0 from fault.memory.intel | |
ARC review is required.