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Date: Wed, 21 Jan 2009 08:50:45 -0800 (PST)
From: "Garrett D'Amore - sun microsystems" <gd78059@sac.sfbay.sun.com>
Subject: prefetch interfaces [PSARC/2009/039 Self Review]
To: PSARC-ext@sun.com
Cc: pdurrant@solarflare.com
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Template Version: @(#)sac_nextcase %I% %G% SMI
This information is Copyright 2009 Sun Microsystems
1. Introduction
    1.1. Project/Component Working Name:
	 prefetch interfaces
    1.2. Name of Document Author/Supplier:
	 Author:  Paul Durrant
    1.3  Date of This Document:
	21 January, 2009
4. Technical Description

I'm sponsoring this case for Paul Durrant.  I believe it qualifies for
self review.  The interfaces proposed (prefetch_read_many and
prefetch_read_once) are proposed for Consolidation Private commitment.
This case seeks Patch binding, although at the moment we believe this
will only be delivered into Nevada.

If anyone thinks it deserves more discussion, please feel free to bump
it up to a regular fast track.

	-- Garrett

PROBLEM

Many device drivers, particularly 10 gigabit network drivers, need to
avoid CPU stalls to achieve good bandwidth. CPU stalls can be caused
by many things including cache and TLB misses. Careful code and data
structure layout can be used to mitigate TLB misses. Cache misses can
also be mitigated by careful code and data layout, but also by giving
hints to the CPU to prefetch certain data into cache many cycles
before that data is required. ON currently lacks interfaces for device
drivers to request prefetch in a platform agnostic way.

PROPOSAL

Add inlines for i386/amd64 and sparcv9 for the following types of prefetch:

void prefetch_read_many(void *)

This requests data be loaded into a cache for repeated reading. (This
equates to a 't0' prefetch on x86 CPUs).

void prefetch_read_once(void *)

This requests data be loaded into a cache for one read only, so it can
be flushed from the cache immediately after access. (This equates to a
'nta' prefetch on x86 CPUs).

6. Resources and Schedule
    6.4. Steering Committee requested information
   	6.4.1. Consolidation C-team Name:
		ON
    6.5. ARC review type: Automatic
    6.6. ARC Exposure: open


From Alan.Coopersmith@sun.com Wed Jan 21 09:27:20 2009
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Date: Wed, 21 Jan 2009 09:27:01 -0800
From: Alan Coopersmith <Alan.Coopersmith@sun.com>
Subject: Re: prefetch interfaces [PSARC/2009/039 Self Review]
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How do these interfaces compare with the sun_prefetch.h ones provided
by Sun Studio?   Is the difference just that these are compiler
independent?

-- 
	-Alan Coopersmith-           alan.coopersmith@sun.com
	 Sun Microsystems, Inc. - X Window System Engineering


From carlsonj@phorcys.east.sun.com Wed Jan 21 09:31:10 2009
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Date: Wed, 21 Jan 2009 12:23:33 -0500
From: James Carlson <james.d.carlson@sun.com>
Subject: Re: prefetch interfaces [PSARC/2009/039 Self Review]
In-reply-to: <200901211650.n0LGojkZ011461@sac.sfbay.sun.com>
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Garrett D'Amore - sun microsystems writes:
> Add inlines for i386/amd64 and sparcv9 for the following types of prefetch:
> 
> void prefetch_read_many(void *)
> 
> This requests data be loaded into a cache for repeated reading. (This
> equates to a 't0' prefetch on x86 CPUs).
> 
> void prefetch_read_once(void *)
> 
> This requests data be loaded into a cache for one read only, so it can
> be flushed from the cache immediately after access. (This equates to a
> 'nta' prefetch on x86 CPUs).

Are there SPARC equivalents?  Have you considered other CPUs?

On PPC, there are four related instructions that I know about:

	dcbt	- data cache block touch
	dcbtst	- data cache block touch for store
	dcbz	- data cache block set to zero
	dcbf	- data cache block flush

The first of those sounds like prefetch_read_many().  The others seem
not to match up ... but *perhaps* they're rare enough (buried within
bcopy and bzero) that nobody cares ... ?

-- 
James Carlson, Solaris Networking              <james.d.carlson@sun.com>
Sun Microsystems / 35 Network Drive        71.232W   Vox +1 781 442 2084
MS UBUR02-212 / Burlington MA 01803-2757   42.496N   Fax +1 781 442 1677

From roland.mainz@nrubsig.org Wed Jan 21 10:06:15 2009
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Date: Wed, 21 Jan 2009 19:06:03 +0100
From: Roland Mainz <roland.mainz@nrubsig.org>
Subject: Re: prefetch interfaces [PSARC/2009/039 Self Review]
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Garrett D'Amore - sun microsystems wrote:
[snip]
> PROPOSAL
> 
> Add inlines for i386/amd64 and sparcv9 for the following types of prefetch:
> 
> void prefetch_read_many(void *)
> 
> This requests data be loaded into a cache for repeated reading. (This
> equates to a 't0' prefetch on x86 CPUs).
> 
> void prefetch_read_once(void *)
> 
> This requests data be loaded into a cache for one read only, so it can
> be flushed from the cache immediately after access. (This equates to a
> 'nta' prefetch on x86 CPUs).

Why do both interfaces do not have a |length| operand ? Some
CPUs/architecturs allow to define a memory range (rounded up to the CPUs
block size) to be pre-fetched...

----

Bye,
Roland

-- 
  __ .  . __
 (o.\ \/ /.o) roland.mainz@nrubsig.org
  \__\/\/__/  MPEG specialist, C&&JAVA&&Sun&&Unix programmer
  /O /==\ O\  TEL +49 641 3992797
 (;O/ \/ \O;)

From bart.smaalders@sun.com Wed Jan 21 11:18:41 2009
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Date: Wed, 21 Jan 2009 11:10:51 -0800
From: Bart Smaalders <bart.smaalders@sun.com>
Subject: Re: prefetch interfaces [PSARC/2009/039 Self Review]
In-reply-to: <200901211650.n0LGojkZ011461@sac.sfbay.sun.com>
To: "Garrett D'Amore - sun microsystems" <gd78059@sac.sfbay.sun.com>
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Garrett D'Amore - sun microsystems wrote:
> ON currently lacks interfaces for device
> drivers to request prefetch in a platform agnostic way.


What about prefetch64()?

-=  Bart

-- 
Bart Smaalders			Solaris Kernel Performance
barts@cyber.eng.sun.com		http://blogs.sun.com/barts
"You will contribute more with mercurial than with thunderbird."

From gdamore@sun.com Wed Jan 21 12:26:43 2009
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From: "Garrett D'Amore" <gdamore@sun.com>
Subject: Re: prefetch interfaces [PSARC/2009/039 Self Review]
In-reply-to: <4977733B.2070804@Sun.COM>
Sender: Garrett.Damore@sun.com
To: Bart Smaalders <Bart.Smaalders@sun.com>
Cc: "Garrett D'Amore - sun microsystems" <gd78059@sac.sfbay.sun.com>,
        PSARC-ext@sun.com, pdurrant@solarflare.com
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Bart Smaalders wrote:
> Garrett D'Amore - sun microsystems wrote:
>> ON currently lacks interfaces for device
>> drivers to request prefetch in a platform agnostic way.
>
>
> What about prefetch64()?
>
> -=  Bart
>

In light of the excellent questions asked (many of which I don't 
personally have answers for, but need to get feedback from Paul on), I'm 
promoting the case to a fast track, with a timeout set for one week from 
today.

    -- Garrett


From pdurrant@solarflare.com Thu Jan 22 01:35:29 2009
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Date: Thu, 22 Jan 2009 09:35:18 +0000
From: Paul Durrant <pdurrant@solarflare.com>
Subject: Re: prefetch interfaces [PSARC/2009/039 Self Review]
In-reply-to: <18807.23061.888203.839588@gargle.gargle.HOWL>
To: James Carlson <james.d.carlson@sun.com>
Cc: "Garrett D'Amore - sun microsystems" <gd78059@sac.sfbay.sun.com>,
        PSARC-ext@sun.com
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James Carlson wrote:
> 
> Are there SPARC equivalents?  Have you considered other CPUs?
> 

Yes and, in fact, the names of the inlines correspond more to the SPARC 
nomenclature. I have implementations for both SPARC and x86.

> On PPC, there are four related instructions that I know about:
> 
> 	dcbt	- data cache block touch
> 	dcbtst	- data cache block touch for store
> 	dcbz	- data cache block set to zero
> 	dcbf	- data cache block flush
> 
> The first of those sounds like prefetch_read_many().  The others seem
> not to match up ... but *perhaps* they're rare enough (buried within
> bcopy and bzero) that nobody cares ... ?
> 

I think the semantics of the inlines are general enough that they should 
apply to most architectures that support pre-fetching.

   Paul

-- 
==============================
Paul Durrant
Senior Staff Engineer
Solarflare Communications Inc.
==============================

From pdurrant@solarflare.com Thu Jan 22 01:38:02 2009
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Date: Thu, 22 Jan 2009 09:37:48 +0000
From: Paul Durrant <pdurrant@solarflare.com>
Subject: Re: prefetch interfaces [PSARC/2009/039 Self Review]
In-reply-to: <4977640B.A74632D0@nrubsig.org>
To: Roland Mainz <roland.mainz@nrubsig.org>
Cc: "Garrett D'Amore - sun microsystems" <gd78059@sac.sfbay.sun.com>,
        PSARC-ext@sun.com
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Roland Mainz wrote:
> 
> Why do both interfaces do not have a |length| operand ? Some
> CPUs/architecturs allow to define a memory range (rounded up to the CPUs
> block size) to be pre-fetched...
> 

Roland,

   The intention is to keep things simple. In case it was not apparent 
from my submission, the intention of the inlines is to pre-fetch single 
cache lines. Also, neither SPARC nor x86 have single prefetch 
instructions to fetch multiple cache lines so a length argument would be 
extraneous at this point. Remember that these interface are intended to 
be undocumented and unstable so any future changes that aid performance 
would be welcome.

   Paul


-- 
==============================
Paul Durrant
Senior Staff Engineer
Solarflare Communications Inc.
==============================

From pdurrant@solarflare.com Thu Jan 22 01:48:23 2009
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Date: Thu, 22 Jan 2009 09:47:19 +0000
From: Paul Durrant <pdurrant@solarflare.com>
Subject: Re: prefetch interfaces [PSARC/2009/039 Self Review]
In-reply-to: <4977733B.2070804@Sun.COM>
To: Bart Smaalders <bart.smaalders@sun.com>
Cc: "Garrett D'Amore - sun microsystems" <gd78059@sac.sfbay.sun.com>,
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Bart Smaalders wrote:
> 
> What about prefetch64()?
> 

Hmm. That was integrated a long time after I did my implementations 
(that's how long I've been waiting to integrate!). It looks like it has 
the right semantics for x86 but the sparc implementation seems to be 
n_writes; I'm not sure what that will do.
I'd be willing to drop this case and go with that interface though if 
the sparc prefetch does what I need (i.e. pull data into cache for 
multiple-read access).

   Paul

-- 
==============================
Paul Durrant
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Solarflare Communications Inc.
==============================

From pdurrant@solarflare.com Thu Jan 22 01:56:42 2009
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Date: Thu, 22 Jan 2009 09:56:33 +0000
From: Paul Durrant <pdurrant@solarflare.com>
Subject: Re: prefetch interfaces [PSARC/2009/039 Self Review]
In-reply-to: <497840A7.1020407@solarflare.com>
To: Bart Smaalders <bart.smaalders@sun.com>
Cc: "Garrett D'Amore - sun microsystems" <gd78059@sac.sfbay.sun.com>,
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Paul Durrant wrote:
> 
> Hmm. That was integrated a long time after I did my implementations 
> (that's how long I've been waiting to integrate!). It looks like it has 
> the right semantics for x86 but the sparc implementation seems to be 
> n_writes; I'm not sure what that will do.
> I'd be willing to drop this case and go with that interface though if 
> the sparc prefetch does what I need (i.e. pull data into cache for 
> multiple-read access).
> 

I found my sparcv9 manual! Prefetching for n_writes apparently implies 
exclusivity of the cache line in the CPU issuing the prefetch so would 
cause unnecessary cache line flushing in my use-case. How about I add 
prefetch_wrote_once() and prefetch_write_many() (the once and many 
mapping to nta amd t0 for x86, as with read) to the set and then change 
the consumers of prefetch64() (of which there only appears to be one) to 
use prefetch_write_many()? That way things continue to work as-is and we 
cover the full set of prefetched on the current set of supported CPUs.

   Paul


-- 
==============================
Paul Durrant
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Solarflare Communications Inc.
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From pdurrant@solarflare.com Thu Jan 22 01:57:35 2009
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Date: Thu, 22 Jan 2009 09:57:26 +0000
From: Paul Durrant <pdurrant@solarflare.com>
Subject: Re: prefetch interfaces [PSARC/2009/039 Self Review]
In-reply-to: <49775AE5.3010201@sun.com>
To: Alan Coopersmith <Alan.Coopersmith@sun.com>
Cc: "Garrett D'Amore - sun microsystems" <gd78059@sac.sfbay.sun.com>,
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Alan Coopersmith wrote:
> How do these interfaces compare with the sun_prefetch.h ones provided
> by Sun Studio?   Is the difference just that these are compiler
> independent?
> 

Yes, you hit the nail on the head. These are not dependent on the 
compiler; they are implemented for gcc as well as studio.

   Paul

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==============================
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==============================

From gdamore@sun.com Tue Mar 17 14:23:02 2009
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Date: Tue, 17 Mar 2009 14:22:55 -0700
From: "Garrett D'Amore" <gdamore@sun.com>
Subject: PSARC 2009/039 prefetch interfaces
Sender: Garrett.Damore@sun.com
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I have to apologize to Paul here, but I neglected to update the IAM file 
to indicate that this is a fast track, so I don't think the "litany" was 
ever run on this case.  I'm updating the IAM file now, and I'm pushing 
the timeout on this to next Wednesday.

However, I believe that all the material concerns were addressed in the 
case history by Paul already, and I don't see why this case can't be 
approved tomorrow.  Can I get a +1 from a member? :-)

    -- Garrett


From carlsonj@phorcys.east.sun.com Tue Mar 17 14:41:26 2009
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Date: Tue, 17 Mar 2009 17:41:13 -0400
From: James Carlson <james.d.carlson@sun.com>
Subject: Re: PSARC 2009/039 prefetch interfaces
In-reply-to: <49C014AF.6040109@sun.com>
To: "Garrett D'Amore" <gdamore@sun.com>
Cc: PSARC-ext <PSARC-ext@sun.com>
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Garrett D'Amore writes:
> I have to apologize to Paul here, but I neglected to update the IAM file 
> to indicate that this is a fast track, so I don't think the "litany" was 
> ever run on this case.  I'm updating the IAM file now, and I'm pushing 
> the timeout on this to next Wednesday.
> 
> However, I believe that all the material concerns were addressed in the 
> case history by Paul already, and I don't see why this case can't be 
> approved tomorrow.  Can I get a +1 from a member? :-)

Can we have a summary of the proposal?  I *think* we currently have
Consolidation Private stability (within ON) and Patch/Micro release
binding for:

void prefetch_read_once(void *)
void prefetch_read_many(void *)
void prefetch_wrote_once(void *)
void prefetch_write_many(void *)

(With the odd write/wrote distinction and with the arguments not
const'd the way I would ordinarily have expected.)

Is this it?

-- 
James Carlson, Solaris Networking              <james.d.carlson@sun.com>
Sun Microsystems / 35 Network Drive        71.232W   Vox +1 781 442 2084
MS UBUR02-212 / Burlington MA 01803-2757   42.496N   Fax +1 781 442 1677

From pdurrant@solarflare.com Wed Mar 18 02:02:37 2009
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Date: Wed, 18 Mar 2009 09:02:26 +0000
From: Paul Durrant <pdurrant@solarflare.com>
Subject: Re: PSARC 2009/039 prefetch interfaces
In-reply-to: <18880.6393.556664.951029@gargle.gargle.HOWL>
To: James Carlson <james.d.carlson@sun.com>
Cc: "Garrett D'Amore" <gdamore@sun.com>, PSARC-ext <PSARC-ext@sun.com>
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James Carlson wrote:
> 
> void prefetch_read_once(void *)
> void prefetch_read_many(void *)
> void prefetch_wrote_once(void *)
> void prefetch_write_many(void *)
> 
> (With the odd write/wrote distinction and with the arguments not
> const'd the way I would ordinarily have expected.)
> 
> Is this it?
> 

It should be prefetch_write_once(void *) and I don't believe const is 
appropriate here since the pointers are most likely to be to data that 
would ordinarily change (DMA buffers in my use case).

   Paul

From carlsonj@phorcys.east.sun.com Wed Mar 18 05:20:50 2009
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Date: Wed, 18 Mar 2009 08:13:08 -0400
From: James Carlson <james.d.carlson@sun.com>
Subject: Re: PSARC 2009/039 prefetch interfaces
In-reply-to: <49C0B8A2.2060807@solarflare.com>
To: Paul Durrant <pdurrant@solarflare.com>
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Paul Durrant writes:
> James Carlson wrote:
> > 
> > void prefetch_read_once(void *)
> > void prefetch_read_many(void *)
> > void prefetch_wrote_once(void *)
> > void prefetch_write_many(void *)
> > 
> > (With the odd write/wrote distinction and with the arguments not
> > const'd the way I would ordinarily have expected.)
> > 
> > Is this it?
> > 
> 
> It should be prefetch_write_once(void *)

That's better.

> and I don't believe const is 
> appropriate here since the pointers are most likely to be to data that 
> would ordinarily change (DMA buffers in my use case).

The function itself doesn't actually cause that to happen, though; the
hardware does.  Even if you didn't mess with the prefetch, these
buffer content changes would *still* appear.  The compiler needn't
assume that the buffer changes as a specific synchronous effect of
that function.

Instead, _your_ code needs to be aware of the fact that there's an
unseen hand that's twiddling the bits, which is the definition of the
'volatile' keyword.  You need 'volatile' on your pointers to generate
correct code, but I don't think these functions need writability to
operate.

In fact, as a very narrow use-case, consider a read-only device.  Your
pointer would be something like "const volatile uchar_t *", to
indicate that your code can't write to it (const) and that references
can't be optimized because it changes in ways not obvious in the code
(volatile).

Anyway, I think that's probably a nit for the prefetch_read_*
functions.  After fixing "wrote" to "write," I'll give it a +1.

-- 
James Carlson, Solaris Networking              <james.d.carlson@sun.com>
Sun Microsystems / 35 Network Drive        71.232W   Vox +1 781 442 2084
MS UBUR02-212 / Burlington MA 01803-2757   42.496N   Fax +1 781 442 1677

From gdamore@sun.com Wed Mar 18 19:40:57 2009
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Date: Wed, 18 Mar 2009 19:40:52 -0700
From: "Garrett D'Amore" <gdamore@sun.com>
Subject: PSARC 2009/039 prefetch interfaces
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This case was approved at PSARC today.

